View ML610Q408P-NNNTBZ03A_3908794.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ml610q407/ml610q408/ml610q409 user?s manual issue date: nov. 7, 2010 feul610q409-01
notice 1. the information contained herein can ch ange without notice owing to product and/or technical improvements. before using the product, please make sure that the inform ation being referred to is up-to-date. 2. the outline of action and examples for a pplication circuits desc ribed herein have been chosen as an explanation for the stan dard action and performance of the product. when pl anning to use the product, please ensure that the external conditions are reflect ed in the actual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not lim ited to, operating voltage, power di ssipation, and operating temperature. 4. oki semiconductor assumes no respon sibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, impr oper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third party?s indus trial and intellectual property ri ght, etc. is granted by us i n connection with the use of the product and/or the information an d drawings contained herein. no responsibility is assumed by us for any infringement of a third party?s righ t which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment fo r commercial applications (e.g. , office automation, communication equipmen t, measurement equipment, consumer electronics, etc. ). these products are not, unless specifically authorized by oki semiconductor authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not li mited to, traffic and automotive equipment, safety devices, aeros pace equipment, nucl ear power control, medical equipm ent, and life-support systems. 7. certain products in this document may need government approv al before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. copyright 2010 oki semiconductor co., ltd.
preface this manual describes the operation of th e hardware of the 8-bit microcontroller ml610q407/ml610q408/ml610q409. the following manuals are also available. read them as necessary. ? nx-u8/100 core instruction manual description on the basic architectur e and the each instruction of the nx-u8/100 core . ? macu8 assembler package user?s manual description on the method of operating the relocatable assembler, the linker, the librarian, and the object conve rter and also on the specif ications of the assembler language. ? ccu8 user?s manual description on the method of operating the compiler . ? ccu8 programming guide description on the method of programming. ? ccu8 language reference description on the language specifications . ? dtu8 debugger user?s manual description on the method of operating the debugger dtu8 . ? ideu8 user?s manual description on the integrated development environment ideu8 . ? uease user?s manual description on the on-chip debug tool uease. ? uease connection manual for ml610q407/ml610q408/ml610q409 description about the conn ection between uease and ml610q407/ ml610q408/ ml610q409 . ? fwuease flash writer host program user?s manual description on the flash writer host program.
notation classification notation description ? numeric value xxh, xxh indicates a hexadecimal number. x: any value in the range of 0 to f xxb indicates a binary number; ?b? may be omitted. x: a value 0 or 1 ? unit word, w 1 word = 16 bits byte, b 1 byte = 8 bits nibble, n 1 nibble = 4 bits maga-, m 10 6 kilo-, k 2 10 = 1024 kilo-, k 10 3 = 1000 milli-, m 10 -3 micro-, 10 -6 nano-, n 10 -9 second, s (lower case) second ? terminology ?h? level, ?1? level indicates high voltage signal levels v ih and v oh as specified by the electrical characteristics. ?l? level, ?0? level indicates low voltage signal levels v il and v ol as specified by the electrical characteristics. ? register description r/w: indicates that read/write attribute. ?r? indicates that data can be read and ?w? indicates that data can be written. ?r/w? indicates that data can be read or written. msb lsb fcon0 ? ? outc1 outc0 oscm1 oscm0 sysc1 sysc0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 1 1 0 1 0 1 bit name register name initial value after reset invalid bit: this bit reads ?0? when re ad. write to this bit is ignored.
ml610q407/ml610q408/ml610q 409 user?s manual contents contents ? 0 table of contents chapter 1 1. overview ................................................................................................................... ........................................................ 1-1 1.1 features ...................................................................................................................... .................................................. 1-1 1.2 configuration of functional blocks ............................................................................................. ................................ 1-4 1.2.1 block diagram of ml610q407/ml610q408/ml610q409......................................................................... ..... 1-4 1.3 pins ...................................................................................................................... ........................................................ 1-5 1.3.1 pin layout.............................................................................................................. ............................................... 1-5 1.3.1.1 pin layout of ml610q407 tq fp pack age ................................................................................. ........................................ 1-5 1.3.1.2 pin layout of ml610q408 tq fp pack age ................................................................................. ........................................ 1-6 1.3.1.3 pin layout of ml610q409 tq fp pack age ................................................................................. ........................................ 1-7 1.3.1.4 pin lay out of ml 610q407 ch ip......................................................................................... ................................................. 1-8 1.3.1.5 pin lay out of ml 610q408 ch ip......................................................................................... ................................................. 1-9 1.3.1.6 pin lay out of ml 610q409 ch ip......................................................................................... ............................................... 1-10 1.3.1.7 pad coordinates of ml610q407/ml610q 408/m610q409 chip ................................................................. ..................... 1-11 1.3.2 list of pins................................................................................................................... ....................................... 1-12 1.3.3 pin descriptions............................................................................................................... ................................... 1-15 1.3.4 handling of unused pins ................................................................................................. ................................... 1-19 chapter 2 2. cpu and memory space ........................................................................................................... ........................................... 2-1 2.1 overview ....................................................................................................................... ............................................... 2-1 2.2 program memory space ........................................................................................................... .................................... 2-1 2.3 data memo ry space .............................................................................................................. ....................................... 2-2 2.4 instruction length............................................................................................................. ............................................ 2-3 2.5 data type ...................................................................................................................... ............................................... 2-3 2.6 description of registers ....................................................................................................... ........................................ 2-4 2.6.1 list of re gisters .............................................................................................................. ...................................... 2-4 2.6.2 data segment re gister (dsr) .................................................................................................... .......................... 2-5 chapter 3 3. reset f unction ................................................................................................................. ..................................................... 3-1 3.1 overview ....................................................................................................................... ............................................... 3-1 3.1.1 features....................................................................................................................... .......................................... 3-1 3.1.2 configuration.................................................................................................................. ...................................... 3-1 3.1.3 list of pins................................................................................................................... ......................................... 3-1 3.2 description of registers ....................................................................................................... ........................................ 3-2 3.2.1 list of re gisters .............................................................................................................. ...................................... 3-2 3.2.2 reset status regi ster (rstat) .................................................................................................. ........................... 3-2 3.3 description of operation ....................................................................................................... ....................................... 3-3 3.3.1 operation of syst em reset mode ................................................................................................. ........................ 3-3
ml610q407/ml610q408/ml610q 409 user?s manual contents contents ?1 chapter 4 4. mcu control function........................................................................................................... .............................................. 4-1 4.1 overview ....................................................................................................................... ............................................... 4-1 4.1.1 features....................................................................................................................... .......................................... 4-1 4.1.2 configuration.................................................................................................................. ...................................... 4-1 4.2 description of registers ....................................................................................................... ........................................ 4-2 4.2.1 list of re gisters .............................................................................................................. ...................................... 4-2 4.2.2 stop code acceptor (stpacp) .................................................................................................... ........................ 4-3 4.2.3 standby control re gister (sbycon) .............................................................................................. .................... 4-4 4.2.4 block control regist er 0 (blkcon0) ............................................................................................. ................... 4-5 4.2.5 block control regist er 1 (blkcon1) ............................................................................................. ................... 4-6 4.2.6 block control regist er 2 (blkcon2) ............................................................................................. ................... 4-7 4.2.7 block control regist er 3 (blkcon3) ............................................................................................. ................... 4-8 4.2.8 block control regist er 4 (blkcon4) ............................................................................................. ................... 4-9 4.3 description of operation ....................................................................................................... ..................................... 4-10 4.3.1 program run mode............................................................................................................... .............................. 4-10 4.3.2 halt mode...................................................................................................................... .................................. 4-10 4.3.3 stop mode...................................................................................................................... ................................... 4-11 4.3.3.1 stop mode when cpu operat es with low-speed clock ............................................................................... .................. 4-11 4.3.3.2 stop mode when cpu operat es with high- speed clock.............................................................................. ................... 4-12 4.3.4 note on return operation from stop/halt mode................................................................................... ....... 4-13 4.3.5 block contro l function ......................................................................................................... ............................. 4-14 chapter 5 5. interrupts..................................................................................................................... .......................................................... 5-1 5.1 overview ....................................................................................................................... ............................................... 5-1 5.1.1 features....................................................................................................................... .......................................... 5-1 5.2 description of registers ....................................................................................................... ........................................ 5-2 5.2.1 list of re gisters .............................................................................................................. ...................................... 5-2 5.2.2 interrupt enable register 1 (ie1).............................................................................................. ............................ 5-3 5.2.3 interrupt enable register 2 (ie2).............................................................................................. ............................ 5-4 5.2.4 interrupt enable register 3 (ie3).............................................................................................. ............................ 5-5 5.2.5 interrupt enable register 4 (ie4).............................................................................................. ............................ 5-6 5.2.6 interrupt enable register 5 (ie5).............................................................................................. ............................ 5-7 5.2.7 interrupt enable register 6 (ie6).............................................................................................. ............................ 5-8 5.2.8 interrupt enable register 7 (ie7).............................................................................................. ............................ 5-9 5.2.9 interrupt request register 0 (irq0)..................................................................................... .............................. 5-10 5.2.10 interrupt request re gister 1 (irq1)............................................................................................ ....................... 5-11 5.2.11 interrupt request re gister 2 (irq2)............................................................................................ ....................... 5-13 5.2.12 interrupt request re gister 3 (irq3)............................................................................................ ....................... 5-14 5.2.13 interrupt request re gister 4 (irq4)............................................................................................ ....................... 5-15 5.2.14 interrupt request re gister 5 (irq5)............................................................................................ ....................... 5-16 5.2.15 interrupt request re gister 6 (irq6)............................................................................................ ....................... 5-17 5.2.16 interrupt request re gister 7 (irq7)............................................................................................ ....................... 5-18 5.3 description of operation ....................................................................................................... ..................................... 5-19 5.3.1 maskable interrupt processing.................................................................................................. .......................... 5-20 5.3.2 non-maskable interrupt processing .............................................................................................. ..................... 5-20 5.3.3 software interrupt processing.................................................................................................. ........................... 5-20 5.3.4 notes on interrupt routine ..................................................................................................... ............................ 5-21 5.3.5 interrupt disa ble state ........................................................................................................ ................................ 5-24
ml610407/ml610408/ml610409 user?s manual contents contents ?2 chapter 6 6. clock generati on circuit....................................................................................................... ............................................... 6-1 6.1 overview ....................................................................................................................... ............................................... 6-1 6.1.1 features....................................................................................................................... .......................................... 6-1 6.1.2 configuration.................................................................................................................. ...................................... 6-1 6.1.3 list of pins................................................................................................................... ......................................... 6-2 6.2 description of registers ....................................................................................................... ........................................ 6-2 6.2.1 list of re gisters .............................................................................................................. ...................................... 6-2 6.2.2 frequency control re gister 0 (fcon0)........................................................................................... .................... 6-3 6.2.3 frequency control re gister 1 (fcon1)........................................................................................... .................... 6-4 6.3 description of operation ....................................................................................................... ....................................... 6-5 6.3.1 low-speed clock ................................................................................................................ ................................. 6-5 6.3.1.1 low-speed cloc k generation circuit .................................................................................... ................................................ 6-5 6.3.1.2 operation of low-sp eed clock genera tion circ uit ....................................................................... ........................................ 6-6 6.3.2 high-speed clock ............................................................................................................... ................................... 6-7 6.3.2.1 high-speed cloc k generation circuit................................................................................... ................................................. 6-7 6.3.2.2 operation of high-sp eed clock genera tion circ uit...................................................................... ......................................... 6-8 6.3.3 switching of sy stem cl ock...................................................................................................... ............................. 6-9 6.4 specifying port registers ...................................................................................................... ..................................... 6-10 6.4.1 functioning p21 (outclk) as the high-speed clock output ........................................................................ .... 6-10 6.4.2 functioning p20 (lsclk) as the low-speed clock output .......................................................................... ....... 6-11 chapter 7 7. time base counter .......................................................................................................... .................................................. 7-1 7.1 overview ....................................................................................................................... ............................................... 7-1 7.1.1 features................................................................................................................. ................................................... 7-1 7.1.2 configuration.................................................................................................................. ...................................... 7-1 7.2 description of registers ....................................................................................................... ........................................ 7-3 7.2.1 list of re gisters .............................................................................................................. ...................................... 7-3 7.2.2 low-speed time base c ounter regist er (ltbr) .................................................................................... ............ 7-4 7.2.3 high-speed time base counter divide regist er (htb dr)........................................................................... ......................... 7-5 7.2.4 low-speed time base counter frequency adjustment registers l and h (ltbadjl, ltbadjh) ........................................................................................................... .......................... 7-6 7.3 description of operation ....................................................................................................... ....................................... 7-7 7.3.1 low-speed time base counter.................................................................................................... ......................... 7-7 7.3.2 high-speed time base counter ................................................................................................... ........................ 7-8 7.3.3 low-speed time base counter fr equency adjustment function...................................................................... .. 7-9 7.3.4 a signal generation for 16-bit timer 2-3 frequency measurement mode............................................................ .7-10 chapter 8 8. capture .................................................................................................................... .......................................................... 8-1 8.1 overview...................................................................................................................... ................................................ 8-1 8.1.1 features................................................................................................................ ................................................. 8-1 8.1.2 configuration........................................................................................................... ............................................. 8-1 8.1.3 list of pins................................................................................................................... ......................................... 8-1 8.2 description of registers ....................................................................................................... ........................................ 8-2 8.2.1 list of registers....................................................................................................... ............................................. 8-2 8.2.2 capture contro l register (capcon) ....................................................................................... ........................... 8-3 8.2.3 capture status register (capstat) ....................................................................................... ............................. 8-4 8.2.4 capture data register 0 (capr0)......................................................................................... ............................... 8-5 8.2.5 capture data register 1 (capr1)......................................................................................... ............................... 8-6
ml610q407/ml610q408/ml610q 409 user?s manual contents contents ?3 8.2.6 capture time base data register (captb)................................................................................. ........................ 8-7 8.3 description of operation ....................................................................................................... ....................................... 8-8 chapter 9 9. timer .......................................................................................................................... .......................................................... 9-1 9.1 overview ....................................................................................................................... ............................................... 9-1 9.1.1 features....................................................................................................................... .......................................... 9-1 9.1.2 configuration.................................................................................................................. ...................................... 9-1 9.1.3 list of pins................................................................................................................... ......................................... 9-2 9.2 description of registers ....................................................................................................... ........................................ 9-3 9.2.1 list of re gisters .............................................................................................................. ...................................... 9-3 9.2.2 timer 0 data register (tm0d) ................................................................................................... ......................... 9-4 9.2.3 timer 1 data register (tm1d) ................................................................................................... ......................... 9-5 9.2.4 timer 2 data register (tm2d) ................................................................................................... ......................... 9-6 9.2.5 timer 3 data register (tm3d) ................................................................................................... ......................... 9-7 9.2.6 timer 0 counter re gister (tm0c) ................................................................................................ ....................... 9-8 9.2.7 timer 1 counter re gister (tm1c) ................................................................................................ ....................... 9-9 9.2.8 timer 2 counter re gister (tm2c) ................................................................................................ ..................... 9-10 9.2.9 timer 3 counter re gister (tm3c) ................................................................................................ ..................... 9-11 9.2.10 timer 0 control regi ster 0 (tm0con0)........................................................................................... .................................... 9-12 9.2.11 timer 1 control regi ster 0 (tm1con0)........................................................................................... .................................... 9-13 9.2.12 timer 2 control regi ster 0 (tm2con0)........................................................................................... .................................... 9-14 9.2.13 timer 3 control regi ster 0 (tm3con0)........................................................................................... .................................... 9-15 9.2.14 timer 0 control regi ster 1 (tm0con1) ........................................................................................... ................ 9-16 9.2.15 timer 1 control regi ster 1 (tm1con1) ........................................................................................... ................ 9-17 9.2.16 timer 2 control regi ster 1 (tm2con1) ........................................................................................... ................ 9-18 9.2.17 timer 3 control regi ster 1 (tm3con1) ........................................................................................... ................ 9-19 9.3 description of operation ....................................................................................................... ..................................... 9-20 9.3.1 timer mode operation........................................................................................................... .............................. 9-20 9.3.2 16-bit timer frequency meas urement mode operation .............................................................................. .......... 9-21 9.3.3 16-bit timer frequency measurement mode a pplication for setting uart baud-rate ............................................. 9-23 9.4 operating timers by ex ternal clock inputs ...................................................................................... ......................... 9-25 9.4.1 operating timer 0 (8-bit ti mer mode) by external clock (p04/t02p0ck)..................................................... 9-25 9.4.2 operating timer 0 (8-bit ti mer mode) by external clock (p44/t02p0ck)..................................................... 9-25 9.4.3 operating timer 1 (8-bit timer mode) by external cloc k (p45/t13ck) ......................................................... 9-26 9.4.4 operating timer 2 (8-bit ti mer mode) by external clock (p04/t02p0ck)..................................................... 9-27 9.4.5 operating timer 2 (8-bit ti mer mode) by external clock (p44/t02p0ck)..................................................... 9-27 9.4.6 operating timer 3 (8-bit timer mode) by external cloc k (p45/t13ck) ......................................................... 9-28 9.4.7 operating timer 0 and timer 1 (16-bit timer mode) by extern al clock (p04/ t02p0ck) .............................. 9-29 9.4.8 operating timer 0 and timer 1 (16-bit timer mode) by extern al clock (p44/ t02p0ck) .............................. 9-29 9.4.9 operating timer 2 and timer 3 (16-bit timer mode) by extern al clock (p44/ t02p0ck) .............................. 9-30 chapter 10 10. pwm....................................................................................................................... ....................................................... 10-1 10.1 overview ....................................................................................................................... ........................................... 10-1 10.1.1 features................................................................................................................ ................................................ 10-1 10.1.2 configuration........................................................................................................... ............................................ 10-1 10.1.3 list of pins................................................................................................................... ....................................... 10-2 10.2 description of registers...................................................................................................... ..................................... 10-2 10.2.1 list of registers...................................................................................................... .......................................... 10-2 10.2.2 pwm0 period registers (pw0pl, pw0ph) ................................................................................... ................. 10-3 10.2.3 pwm0 duty registers (pw0dl, pw0dh) ..................................................................................... ................ 10-4 10.2.4 pwm0 counter re gisters (pw0ch, pw0cl).................................................................................. ............... 10-5 10.2.5 pwm0 control re gister 0 (pw0con0) ...................................................................................... .................... 10-6
ml610407/ml610408/ml610409 user?s manual contents contents ?4 10.2.6 pwm0 control re gister 1 (pw0con1) ...................................................................................... .................... 10-7 10.3 description of operation ....................................................................................................... ................................... 10-8 10.4 specifying por t regist ers ..................................................................................................... ................................... 10-10 10.4.1 functioning the p43 pi n (pwm0) as the pwm output....................................................................... ............ 10-10 10.4.2 functioning the p24 pi n (pwm0) as the pwm output....................................................................... ............ 10-11 10.4.3 operating pwm0 with external clock (p04/t02p0ck)....................................................................... ......... 10-12 10.4.4 operating pwm0 with external clock (p44/t02p0ck)....................................................................... ......... 10-13 chapter 11 11. watchdog timer............................................................................................................ ................................................. 11-1 11.1 overview ....................................................................................................................... ........................................... 11-1 11.1.1 features............................................................................................................... .............................................. 11-1 11.1.2 configuration .......................................................................................................... .......................................... 11-1 11.2 description of registers ....................................................................................................... .................................... 11-2 11.2.1 list of registers ...................................................................................................... .......................................... 11-2 11.2.2 watchdog timer cont rol register (wdtcon) ............................................................................... ................ 11-3 11.2.3 watchdog timer mode register (wdtmod) .................................................................................. ............... 11-4 11.3 description of operation ....................................................................................................... ................................... 11-5 11.3.1 handling example when you do not want to use the watch dog timer ...................................................... ......11- chapter 12 12 synchronous serial port ..................................................................................................... ............................................... 12-1 12.1 o verview ............................................................................................................................... .................................... 12-1 12.1.1 features................................................................................................................ ................................................ 12-1 12.1.2 configuration.................................................................................................................. .................................... 12-1 12.1.3 list of pins................................................................................................................... ....................................... 12-2 12.2 description of registers ....................................................................................................... ...................................... 12-2 12.2.1 list of re gisters .............................................................................................................. .................................... 12-2 12.2.2 serial port 0 transmit/receive buff ers (sio0bufl and sio0bufh).............................................................. 12- 3 12.2.3 serial port 1 transmit/receive buff ers (sio1bufl and sio1bufh).............................................................. 12- 4 12.2.4 serial port 0 contro l register (sio0con) ....................................................................................... ................. 12-5 12.2.5 serial port 1 control register (sio1con)....................................................................................... .................. 12-5 12.2.6 serial port 0 mode re gister 0 (sio0mod0) ....................................................................................... .............. 12-6 12.2.7 serial port 1 mode re gister 0 (sio1mod0) ....................................................................................... .............. 12-7 12.2.8 serial port 0 mode re gister 1 (sio0mod1) ....................................................................................... .............. 12-8 12.2.9 serial port 1 mode re gister 1 (sio1mod1) ....................................................................................... .............. 12-9 12.3 description of operation ....................................................................................................... ................................... 12-10 12.3.1 transmit operation ..................................................................................................... .................................... 12-10 12.3.2 receive operation ...................................................................................................... .................................... 12-12 12.3.3 transmit/receive operation ............................................................................................. .............................. 12-14 12.4 specifying port registers ...................................................................................................... ..................................... 12-15 12.4.1 functioning p42 (sout0: output), p41 (sck0: input/output), and p40 (sin0: input) as the ssio0/ ?master mode?.................................................................................................................. ............................................ 12-15 12.4.2 functioning p42 (sout0: output), p41 (sck 0: input/output), and p40 (sin0: input) as the ssio0/ ?slave mode? ............................................................................................................ ....................................... 12-16 12.4.3 functioning p46 (sout0: output), p45 (sck 0: input/output) and p44 (sin0 : input) as the ssio0/ ?maste r mode? ........................................................................................................... ...................................... 12-17 12.4.4 functioning p46 (sout0: output), p45 (sck 0: input/output) and p44 (sin0 : input) as the ssio0/ ?slave mode? ............................................................................................................ ....................................... 12-18 12.4.5 functioning p52 (sout1: output), p51 (sck1: input/output), and p50 (sin1: input) as the ssio1/ ?master mode?.................................................................................................................. ............................................ 12-19 12.4.6 functioning p52 (sout1: output), p51 (sck 1: input/output), and p50 (sin1: input) as the
ml610q407/ml610q408/ml610q 409 user?s manual contents contents ?5 ssio1/ ?slave mode? ............................................................................................................ ....................................... 12-20 12.4.7 functioning p56 (sout1: output), p55 (sck1: input/output), and p54 (sin1: input) as the ssio1/ ?master mode?.................................................................................................................. ............................................ 12-21 12.4.8 functioning p56 (sout1: output), p55 (sck 1: input/output), and p54 (sin1: input) as the ssio1/ ?slave mode? ............................................................................................................ ....................................... 12-22 chapter 13 13. uart..................................................................................................................... ...................................................... 13-1 13.1 overview ....................................................................................................................... ............................................. 13-1 13.1.1 features................................................................................................................ ................................................ 13-1 13.1.2 configuration.................................................................................................................. .................................... 13-1 13.1.3 list of pins................................................................................................................... ....................................... 13-2 13.2 description of registers ....................................................................................................... ...................................... 13-2 13.2.1 list of re gisters .............................................................................................................. .................................... 13-2 13.2.2 uart0 transmit/receive buffer (ua0buf) ......................................................................................... ........... 13-3 13.2.3 uart0 control regi ster (ua0con) ................................................................................................ ................ 13-4 13.2.4 uart0 mode regist er 0 (ua0mod0) ................................................................................................ ............. 13-5 13.2.5 uart0 mode regist er 1 (ua0mod1) ................................................................................................ ............. 13-6 13.2.6 uart0 baud rate registers l, h (ua0brtl, ua0brth) ............................................................................ 13 -8 13.2.7 uart0 status register (ua0stat) ........................................................................................ ........................ 13-9 13.3 description of operation ....................................................................................................... ................................... 13-11 13.3.1 transfer data format................................................................................................... ................................... 13-11 13.3.2 baud rate.............................................................................................................. ........................................... 13-12 13.3.3 transmitted data direction............................................................................................. ................................ 13-13 13.3.4 transmit operation ..................................................................................................... .................................... 13-14 13.3.5 receive operation ...................................................................................................... .................................... 13-16 13.3.5.1 detecti on of start bit............................................................................................... ......................................................... 13-18 13.3.5.2 samp ling ti ming ...................................................................................................... ........................................................ 13-18 12.3.5.3 recei ve margin ....................................................................................................... ......................................................... 13-19 13.4 specifying port registers...................................................................................................... ..................................... 13-20 13.4.1 functioning p43(txd0) and p42(rxd0) as the uart ........................................................................ ........ 13-20 13.4.2 functioning p43(txd0) and p02(rxd0) as the uart ........................................................................ ........ 13-21 chapter 14 14. port 0 .................................................................................................................... ......................................................... 14-1 14.1 overview....................................................................................................................... ............................................ 14-1 14.1.1 features............................................................................................................... .............................................. 14-1 14.1.2 configuration.................................................................................................................. .................................... 14-1 14.1.3 list of pins................................................................................................................... ....................................... 14-1 14.2 description of registers ....................................................................................................... ...................................... 14-2 14.2.1 list of re gisters .............................................................................................................. .................................... 14-2 14.2.2 port 0 data re gister (p0d) ..................................................................................................... ............................ 14-3 14.2.3 port 0 control registers 0, 1 (p0con0, p0con1)................................................................................. ........... 14-4 14.2.4 external interrupt control regi sters 0, 1 (exicon0, exicon1) ................................................................... . 14-5 14.2.5 external interrupt contro l register 2 (exicon2)................................................................................ ............. 14-6 14.3 description of operation ....................................................................................................... ..................................... 14-7 14.3.1 external interrupt / secondary function................................................................................ ........................... 14-7 14.3.2 interrupt request ...................................................................................................... ........................................ 14-7 chapter 15 15. port 2 .................................................................................................................... ......................................................... 15-1 15.1 overview....................................................................................................................... ............................................ 15-1
ml610407/ml610408/ml610409 user?s manual contents contents ?6 15.1.1 features....................................................................................................................... ........................................ 15-1 15.1.2 configuration.................................................................................................................. .................................... 15-1 15.1.3 list of pins................................................................................................................... ....................................... 15-1 15.2 description of registers ....................................................................................................... ...................................... 15-2 15.2.1 list of re gisters .............................................................................................................. .................................... 15-2 15.2.2 port 2 data re gister (p2d) ..................................................................................................... ............................ 15-3 15.2.3 port 2 control registers 0, 1 (p2con0, p2con1)................................................................................. ........... 15-4 15.2.4 port 2 mode re gister (p2mod)................................................................................................... ...................... 15-5 15.3 description of operation ....................................................................................................... ..................................... 15-6 15.3.1 output port function ................................................................................................... ..................................... 15-6 15.3.2 secondary function ..................................................................................................... ..................................... 15-6 chapter 16 16. port 3 .................................................................................................................... ......................................................... 16-1 16.1 overview....................................................................................................................... ............................................ 16-1 16.1.1 features....................................................................................................................... ........................................ 16-1 16.1.2 configuration.................................................................................................................. .................................... 16-1 16.1.3 list of pins................................................................................................................... ....................................... 16-1 16.2 description of registers ....................................................................................................... ...................................... 16-2 16.2.1 list of re gisters .............................................................................................................. .................................... 16-2 16.2.2 port 3 data register (p3d) ..................................................................................................... ............................. 16-3 16.2.3 port 3 direction re gister (p3dir).............................................................................................. ........................ 16-4 16.2.4 port 3 control registers 0, 1 (p3con0, p3con1)................................................................................. ........... 16-5 16.2.5 port 3 mode regi ster 0 (p3mod0)................................................................................................ .................... 16-7 16.3 description of operation ....................................................................................................... ..................................... 16-9 16.3.1 input/output port functions ............................................................................................ ................................. 16-9 16.3.2 secondary function ..................................................................................................... ..................................... 16-9 chapter 17 17. port 4 .................................................................................................................... ......................................................... 17-1 17.1 overview....................................................................................................................... ............................................ 17-1 17.1.1 features....................................................................................................................... ........................................ 17-1 17.1.2 configuration.................................................................................................................. .................................... 17-1 17.1.3 list of pins................................................................................................................... ....................................... 17-2 17.2 description of registers ....................................................................................................... .................................. 17-3 17.2.1 list of re gisters .............................................................................................................. .................................... 17-3 17.2.2 port 4 data re gister (p4d) ..................................................................................................... ............................ 17-4 17.2.3 port 4 direction re gister (p4dir).............................................................................................. ........................ 17-5 17.2.4 port 4 control registers 0, 1 (p4con0, p4con1)................................................................................. ........... 17-6 17.2.5 port 4 mode registers 0, 1 (p4mod0, p4mod1).................................................................................... ......... 17-8 17.3 description of operation ....................................................................................................... ................................... 17-11 17.3.1 input/output port functions ............................................................................................ ............................... 17-11 17.3.2 secondary and tertiary functions ....................................................................................... ............................. 17-11 chapter 18 18. port 5 .................................................................................................................... ......................................................... 18-1 18.1 overview ....................................................................................................................... ............................................. 18-1 18.1.1 features................................................................................................................ ................................................ 18-1 18.1.2 configuration.................................................................................................................. .................................... 18-1 18.1.3 list of pins................................................................................................................... ....................................... 18-2 18.2 description of registers ....................................................................................................... ...................................... 18-2 18.2.1 list of re gisters .............................................................................................................. .................................... 18-2
ml610q407/ml610q408/ml610q 409 user?s manual contents contents ?7 18.2.2 port 5 data re gister (p5d) ..................................................................................................... ............................ 18-3 18.2.3 port 5 direction re gister (p5dir).............................................................................................. ........................ 18-4 18.2.4 port 5 control registers 0 and 1 (p5con0 and p5con1) ........................................................................... ..... 18-5 18.2.5 port 5 mode register 0 a nd 1 (p5mod0 and p5mod1)............................................................................... .... 18-7 18.2.6 port 5 interrupt mode register (p5isel) ........................................................................................ ................... 18-9 18.3 description of operation ....................................................................................................... ................................... 18-10 18.3.1 input/output port functions ............................................................................................ ............................... 18-10 18.3.2 secondary and tertiary functions ....................................................................................... ............................ 18-10 18.3.3 external interrupt..................................................................................................... ....................................... 18-10 18.3.4 interrupt request ...................................................................................................... ...................................... 18-11 chapter 19 19. port 6 .................................................................................................................... ......................................................... 19-1 19.1 general desc ription ............................................................................................................ ........................................ 19-1 19.1.1 features................................................................................................................ ................................................ 19-1 19.1.2 configuration.................................................................................................................. .................................... 19-1 19.1.3 list of pins................................................................................................................... ....................................... 19-1 19.2 description of registers ....................................................................................................... ...................................... 19-2 19.2.1 list of re gisters .............................................................................................................. .................................... 19-2 19.2.2 port 6 data re gister (p6d) ..................................................................................................... ............................ 19-3 19.2.3 port 6 control regi ster 0 (p6con0)............................................................................................. ..................... 19-4 19.3 description of operation....................................................................................................... .................................... 19-5 19.3.1 output port function ........................................................................................................... ............................... 19-5 chapter 20 20. melody driver .............................................................................................................. .................................................... 20-1 20.1 overview....................................................................................................................... ............................................ 20-1 20.1.1 features....................................................................................................................... ........................................ 20-1 20.1.2 configuration.................................................................................................................. .................................... 20-1 20.1.3 list of pins................................................................................................................... ....................................... 20-1 20.2 description of registers....................................................................................................... ..................................... 20-2 20.2.1 list of re gisters .............................................................................................................. .................................... 20-2 20.2.2 melody 0 control re gister (md0con) ............................................................................................. ................ 20-3 20.2.3 melody 0 tempo code register (md0tmp) .......................................................................................... ........... 20-4 20.2.4 melody 0 scale code register (md0ton) .......................................................................................... ............. 20-5 20.2.5 melody 0 tone length c ode register (md0len) .................................................................................... ........ 20-6 20.3 description of operation ....................................................................................................... ..................................... 20-7 20.3.1 operation of melody output ............................................................................................. ............................... 20-7 20.3.2 tempo codes .................................................................................................................... .................................. 20-8 20.3.3 tone length codes .............................................................................................................. ............................... 20-9 20.3.4 scale codes.................................................................................................................... ................................... 20-10 20.3.5 example of using melody circuit................................................................................................ .................... 20-11 20.3.6 operations of buzzer output .................................................................................................... ........................ 20-12 20.4 specifying port registers ...................................................................................................... ................................... 20-13 20.4.1 functioning p22 pin (md0: output) as the melody or buzzer output ............................................................ 20- 13 20.4.2 functioning p50 pin (md0: output) as the melody or buzzer output ............................................................ 20- 14 chapter 21 21. rc oscillation type a/d converter ............................................................................................. ................................ 21-1 21.1 overview....................................................................................................................... ............................................ 21-1 21.1.1 features....................................................................................................................... ........................................ 21-1 21.1.2 configuration.................................................................................................................. .................................... 21-1
ml610407/ml610408/ml610409 user?s manual contents contents ?8 21.1.3 list of pins................................................................................................................... ....................................... 21-2 21.2 description of registers ....................................................................................................... ...................................... 21-3 21.2.1 list of re gisters .............................................................................................................. .................................... 21-3 21.2.2 rc-adc counter a re gisters (radca0?1).......................................................................................... ........... 21-4 21.2.3 rc-adc counter b re gisters (radcb0?1).......................................................................................... ........... 21-5 21.2.4 rc-adc mode regi ster (radmod) .................................................................................................. ............. 21-6 21.2.5 rc-adc control re gister (radcon) ............................................................................................... .............. 21-7 21.3 description of operation ....................................................................................................... ..................................... 21-8 21.3.1 rc oscillator circu its......................................................................................................... ................................ 21-8 21.3.2 counter a/counter b reference modes ............................................................................................ ............... 21-11 21.3.3 example of use of rc osc illation type a/ d converter ............................................................................ ...... 21-14 21.3.4 monitoring rc oscilla tion ...................................................................................................... ......................... 21-18 21.4 specifying port registers ...................................................................................................... ................................... 21-19 21.4.1 functioning p35(rcm), p34(rct0), p33(rt0), p32(rs0), p31(cs0) and p30(in0) as the rc-adc(ch0).................................................................................................................... .......................................... 21-19 21.4.2 functioning p47(rt1), p46(rs1), p45(cs1) and p44(in1) as the rc-adc(ch1) ........................................ 21-20 chapter 22 22. lcd driver................................................................................................................ .................................................... 22-1 22.1 overview ...................................................................................................................... ............................................ 22-1 22.1.1 features................................................................................................................ ................................................ 22-3 22.1.2 configuration of the lcd drivers........................................................................................ ............................... 22-3 22.1.3 configuration of the bias generati on circuit............................................................................ .......................... 22-4 22.1.4 list of pins................................................................................................................... ....................................... 22-6 22.2 description of registers ....................................................................................................... ...................................... 22-8 22.2.1 list of re gisters .............................................................................................................. .................................... 22-8 22.2.2 bias circuit contro l register 0 (biascon) ............................................................................... ....................... 22-9 22.2.3 display mode re gister 0 (dspmod0) ....................................................................................... ...................... 22-10 22.2.4 display mode re gister 1 (dspmod1) ....................................................................................... ...................... 22-11 22.2.5 display contro l register (dspcon) ....................................................................................... ......................... 22-12 22.2.6 display allocation regist er a (ds0c0a to ds39c4a)....................................................................... ............ 22-13 22.2.7 display allocation regist er b (ds39c4b to ds49c7b)...................................................................... ............ 22-15 22.2.8 display register s (dspr00 to dspr27) .................................................................................... ...................... 22-17 22.3 description of operation ....................................................................................................... ................................... 22-19 22.3.1 operation of lcd drivers and bias genera tion circuit .................................................................... ............... 22-19 22.3.2 segment mapping when the programmable di splay allocation function is not used ................................... 22-20 22.3.3 segment mapping when the programmable display allocation f unction is used .......................................... 22-21 22.3.4 common output waveforms................................................................................................. ............................ 22-22 22.3.5 segment output waveform ................................................................................................. .............................. 22-23 chapter 23 23. power supply circuit.......................................................................................................... .......................................... 23-1 23.1 overview....................................................................................................................... ............................................ 23-1 23.1.1 features....................................................................................................................... ........................................ 23-1 23.1.2 configuration.................................................................................................................. .................................... 23-1 23.1.3 list of pins................................................................................................................... ....................................... 23-1 chapter 24 24. on-chip debug function ......................................................................................................... ...................................... 24-1 24.1 overview ...................................................................................................................... ............................................ 24-1 24.2 method of connecting to on-chip debug emulator................................................................................ ................ 24-1 24.3 flash memory re write function ................................................................................................. ............................. 24-2
ml610q407/ml610q408/ml610q 409 user?s manual contents contents ?9 chapter 25 25. m ask rom version emulation function ............................................................................................. .......................... 25-1 25.1 overview ...................................................................................................................... ............................................ 25-1 25.2 method of connecting to on-chip debug emulator................................................................................ ................ 25-1 25.3 notice for the software program development ................................................................................... ..................... 25-2 25.3.1 notice for the mask rom ve rsion mode setting data .............................................................................. .......... 25-2 25.3.2 notice for the mask rom ve rsion mode me mory size ............................................................................... .... 25-10 25.4 the detail specification of mask rom version mode ............................................................................. ............ 25-11 appendixes appendix a registers ..................................................................................................................... ..................................... a-1 appendix b package dimensions............................................................................................................. ........................... b-1 appendix c electrical char acteris tics ..................................................................................................... ............................ c-1 appendix d application circ uit example.................................................................................................... ....................... d-1 appendix e check list..................................................................................................................... ....................................e-1
ml610407/ml610408/ml610409 user?s manual contents contents ?10
chapter 1 overview
ml610q407/ml610q408/ml610q409 user's manual chapter 1 overview 1-1 1. overview 1.1 features this lsi is a high performance cmos 8-bit microcontroller equipped with an 8-bit cpu nx-u8/100 and integrated with peripheral functions such as the synchr onous serial port, uart, melody driver , rc oscillation type a/d converter, and lcd driver. the cpu nx-u8/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by 3-stage pipe line architecture parallel processing. additionally, it adopts the low-/high-speed dual clock system, standby mode, and process that prohibits leak current at high temperatures, and is most suitable for battery-driven applications. mtp version can rewrite programs on-board, which can contri bute to reduction in product development tat. the flash memory incorporated into this mtp version implements the mask rom-equivalent low-voltage operation (1.2v or higher) and low-power consumption (typically 5ua at low-speed operation), enabling volume production by the mtp version. for industrial use, ml610q407p/ml610q408p /ml610q409p with the extended operating ambient temperature ranging from -40c to 85c are available. z cpu - 8-bit risc cpu (cpu name: nx-u8/100) - instruction system: 16-bit length instruction - instruction set: transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations, bit logic operations, jump, conditional jump , call return stack manipulations, arithmetic shift, and so on - on-chip debug function - minimum instruction execution time 30.5 s (at 32.768 khz system clock) 2 s (at 500 khz system clock) 0.5 s (at 2 mhz system clock) z internal memory - internal 16kbyte flash memory (8k x 16 bits) (including unusable 1kbyte test area) - internal 1kbyte ram (1024 x 8 bits) z interrupt controller - 1 non-maskable interrupt source: internal source: 1 (watchdog timer) - 27 maskable interrupt sources: internal source: 14 (synchronous serial port 0, synchronous serial port 1, timer 0, timer 1, timer 2, timer 3, uart0, melody 0, rc oscillation type a/d converter, pwm0, t bc128hz, tbc32hz, tbc16hz, tbc2hz) external source: 13 (p00, p01, p02, p03, p04, p50, p51, p52, p53, p54, p55, p56, p57) * *: for p50 to p57, the interrupt sources are ored into a single interrupt request. z time base counter - low-speed time base counter x 1 channel frequency compensation (compens ation range: approx. -488ppm to +488ppm. compensation accuracy: approx. 0.48ppm) - high-speed time base counter x 1 channel z watchdog timer - non-maskable interrupt and reset - free running - overflow period: 4 types selectable (125ms, 500ms, 2s, 8s)
ml610q407/ml610q408/ml610q409 user's manual chapter 1 overview 1-2 z timer - 8 bits x 4 channels [also available is 16-bit configurati on (using timers 0 and 1, or timers 2 and 3) x 2 channels] - clock frequency measurement function mode (16-bit c onfiguration using timers 2 and 3 x 1 channel only) z capture - time base capture x 2 channels (4096 hz to 32 hz) z pwm - resolution 16 bits x 1 channel z synchronous serial port - master/slave selectable x 2 channels - lsb first/msb first selectable - 8-bit length/16-bit length selectable z uart - txd/rxd 1 channel - bit length, parity/no pa rity, odd parity/even parity , 1 stop bit/2 stop bits - positive logic/negative logic selectable - built-in baud rate generator z melody driver - scale: 29 types (melody sound frequency: 508 hz to 32.768 khz) - tone length: 63 types - tempo: 15 types - buzzer output mode (4 output mode s, 8 frequencies, 16 duty levels) z rc oscillation type a/d converter - 16-bit counter - time division x 2 channels z general-purpose port - input-only port: 5 channels (i ncluding secondary functions) - output-only port ml610q407: 12 channels (incl uding secondary functions) ml610q408: 8 channels (including secondary functions) ml610q409: 4 channels (including secondary functions) - input/output port: 22 channels (including secondary functions) z lcd driver number of segments ml610q407: up to 145 dots (select among 29 segments x 5 commons, 30 segments x 4 commons, 31 segments x 3 commons, and 32 segments x 2 commons) ml610q408: up to 165 dots (select among 33 segments x 5 commons, 34 segments x 4 commons, 35 segments x 3 commons, and 36 segments x 2 commons) ml610q409: up to 185 dots (select among 37 segments x 5 commons, 38 segments x 4 commons, 39 segments x 3 commons, and 40 segments x 2 commons) - 1/1 to 1/5 duty - 1/2 or 1/3 bias (built-in bias generation circuit) - frame frequency selectable (appr ox. 64 hz, 73 hz, 85 hz, and 102 hz) - bias voltage multiplying clock selectable (8 types) - lcd drive stop mode, lcd display mode, all lcds on mode, and all lcds off mode selectable - programmable display allocation function z reset - reset through the reset_n pin - power-on reset generation when powered on - reset when oscillation stop of the low-speed clock is detected - reset by the watchdog timer (wdt) overflow
ml610q407/ml610q408/ml610q409 user's manual chapter 1 overview 1-3 z clock - low-speed clock (operation of this lsi is not guaranteed under a condition with no supply of low-speed crystal oscillation clock) crystal oscillation (32.768 khz) - high-speed clock built-in rc oscillation (500 khz/2 mhz selectable by software) z power management - halt mode: suspends the instruction execution by cpu (peripheral circuits are in operating states) - stop mode: stops the low-speed oscillation and high-speed oscillation (operations of cpu and peripheral circuits are stopped.) - high-speed clock gear: the frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the oscillation clock) - block control function: completely stops the operation of any function block circuit that is not used (resets registers and stops clock) z shipment ? chip (die) ml610q407-xxxwa ml610q408-xxxwa ml610q409-xxxwa ml610q407p-xxxwa ml610q408p-xxxwa ml610q409p-xxxwa ? 100-pin plastic tqfp ml610q407-xxxtbz03a ml610q408-xxxtbz03a ml610q409-xxxtbz03a ml610q407p-xxxtbz03a ml610q408p-xxxtbz03a ml610q409p-xxxtbz03a xxx: rom code number (xxx of the blank product is nnn) q: mtp version p: wide range temperature version (p version) wa: chip (die) tbz03a: tqfp z guaranteed operation range ? operating temperature: -20c to +70c (p version: -40c to +85c) ? operating voltage: v dd = 1.25v to 3.6v
ml610q407/ml610q408/ml610q409 user's manual chapter 1 overview 1-4 1.2 configuration of functional blocks 1.2.1 block diagram of ml610q407/ml610q408/ml610q409 * secondary function or tertiary function ?*1?: select among 29 segments x 5 commons, 30 s egments x 4 commons, 31 segments x 3 commons, and 32 segments x 2 commons with the register ?*2?: select among 33 segments x 5 commons, 34 s egments x 4 commons, 35 segments x 3 commons, and 36 segments x 2 commons with the register ?*3?: select among 37 segments x 5 commons, 38 s egments x 4 commons, 39 segments x 3 commons, and 40 segments x 2 commons with the register figure 1-1 block diagram of ml610q407/ml610q408/ml610q409 program memory (flash) 16kbyte ram 1kbyte interrupt controller cpu (nx-u8/100) timing controller ea sp on-chip ice instruction decoder bus controller instruction register tbc int 4 int 1 wdt int 4 8bit timer 4 capture 2 gpio int 6 data-bus melody/ buzzer int 1 md0* test0 reset_n osc xt0 xt1 lsclk* outclk* power v ddl lcd driver lcd bias v l1 , v l2 , v l3 c1 , c2 rc-adc 2 cs0* in0* rs0* rt0* crt0* rcm* cs1* in1* rs1* rt1* reset & test alu epsw1 ? 3 psw elr1 ? 3 lr ecsr1 ? 3 dsr/csr pc greg 0 ? 15 v pp v dd v ss int 1 display register 320bit display allocation ram com0 to com4 ( *1 )( *2 )( *3 ) seg0 to seg31 (ml610q407) (*1) seg0 to seg35 (ml610q408) (*2) seg0 to seg39 ( ml6104q09 ) ( *3 ) p00 to p04 p20 to p22 , p24 p30 to p35 p40 to p47 p50 to p53 p60 to p67 (ml610q407) p60 to p63 (ml610q408) ssio 2 sck0* sin0* sout0* int 2 sck1* sin1* sout1* uart int 1 int 1 pwm rxd0* txd0* pwm0* test1_n
ml610q407/ml610q408/ml610q409 user's manual chapter 1 overview 1-5 1.3 pins 1.3.1 pin layout 1.3.1.1 pin layout of ml610q407 tqfp package (nc): no connection note: the assignment of the pads p30 to p35 are not in order. figure 1-2 pin layout of ml610q407 package 12 1 2 3 4 5 6 7 8 9 11 64 65 66 67 68 69 70 71 72 73 74 75 29 28 27 26 99 100 (nc) (nc) p52 (nc) (nc) (nc) 10 14 13 16 15 18 17 20 19 22 21 24 23 25 98 v pp 97 p53 96 p54 95 p55 94 p56 93 p57 92 p35 91 p33 90 p32 89 p34 88 p31 87 p30 86 p04 85 p03 84 p02 83 p01 82 p00 81 p24 80 p22 79 p21 78 p20 77 v ss 76 (nc) (nc) seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 com4/seg2 com3/seg1 com2/seg0 com1 com0 c2 c1 (nc) (nc) p60 p61 p62 p63 p64 p65 p66 p67 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 (nc) 32 31 30 35 34 33 38 37 36 41 40 39 44 43 42 47 46 45 50 49 48 53 54 55 56 57 58 59 60 61 62 63 51 52 p51 p50 p40 p41 p42 p43 p44 p45 p46 p47 v dd v ss v ddl (nc) xt0 xt1 reset_n test0 test1_n v l1 v l2 v l3 (nc)
ml610q407/ml610q408/ml610q409 user's manual chapter 1 overview 1-6 1.3.1.2 pin layout of ml610q408 tqfp package (nc): no connection note: the assignment of the pads p30 to p35 are not in order. figure 1-3 pin layout of ml610q408 package 12 1 2 3 4 5 6 7 8 9 11 64 65 66 67 68 69 70 71 72 73 74 75 29 28 27 26 99 100 (nc) (nc) p52 (nc) (nc) (nc) 10 14 13 16 15 18 17 20 19 22 21 24 23 25 98 v pp 97 p53 96 p54 95 p55 94 p56 93 p57 92 p35 91 p33 90 p32 89 p34 88 p31 87 p30 86 p04 85 p03 84 p02 83 p01 82 p00 81 p24 80 p22 79 p21 78 p20 77 v ss 76 (nc) (nc) seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 com4/seg2 com3/seg1 com2/seg0 com1 com0 c2 c1 (nc) (nc) p60 p61 p62 p63 seg35 seg34 seg33 seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 (nc) 32 31 30 35 34 33 38 37 36 41 40 39 44 43 42 47 46 45 50 49 48 53 54 55 56 57 58 59 60 61 62 63 51 52 p51 p50 p40 p41 p42 p43 p44 p45 p46 p47 v dd v ss v ddl (nc) xt0 xt1 reset_n test0 test1_n v l1 v l2 v l3 (nc)
ml610q407/ml610q408/ml610q409 user's manual chapter 1 overview 1-7 1.3.1.3 pin layout of ml610q409 tqfp package (nc): no connection note: the assignment of the pads p30 to p35 are not in order. figure 1-4 pin layout of ml610q409 package 12 1 2 3 4 5 6 7 8 9 11 64 65 66 67 68 69 70 71 72 73 74 75 29 28 27 26 99 100 (nc) (nc) p52 (nc) (nc) (nc) 10 14 13 16 15 18 17 20 19 22 21 24 23 25 98 v pp 97 p53 96 p54 95 p55 94 p56 93 p57 92 p35 91 p33 90 p32 89 p34 88 p31 87 p30 86 p04 85 p03 84 p02 83 p01 82 p00 81 p24 80 p22 79 p21 78 p20 77 v ss 76 (nc) (nc) seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 com4/seg2 com3/seg1 com2/seg0 com1 com0 c2 c1 (nc) (nc) seg39 seg38 seg37 seg36 seg35 seg34 seg33 seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 (nc) 32 31 30 35 34 33 38 37 36 41 40 39 44 43 42 47 46 45 50 49 48 53 54 55 56 57 58 59 60 61 62 63 51 52 p51 p50 p40 p41 p42 p43 p44 p45 p46 p47 v dd v ss v ddl (nc) xt0 xt1 reset_n test0 test1_n v l1 v l2 v l3 (nc)
ml610q407/ml610q408/ml610q409 user's manual chapter 1 overview 1-8 1.3.1.4 pin layout of ml610q407 chip note: the assignment of the pads p30 to p35 are not in order. chip size: 2.27 mm 2.23 mm pad count: 88 pins minimum pad pitch: 80 m pad aperture: 70 m70 m chip thickness: 350 m voltage of the rear side of chip: v ss level. figure 1-5 dimensions of ml610q407 chip 64 65 66 29 28 27 26 v pp p53 p54 p55 p56 p57 p35 p33 p32 p34 88 p31 87 p30 86 p04 85 p03 84 p02 83 p01 82 p00 81 p24 80 p22 79 p21 78 p20 77 v ss seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 com4/seg2 com3/seg1 com2/seg0 com1 com0 c2 c1 p60 p61 p62 p63 p64 p65 p66 p67 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 32 31 30 35 34 33 38 37 36 41 40 39 44 43 42 53 54 55 56 57 58 59 60 61 62 63 51 52 12 1 2 3 4 5 6 7 8 9 11 10 13 14 15 p52 p51 p50 p40 p41 p42 p43 p44 p45 p46 p47 v dd v ss v ddl xt0 xt1 reset_n test0 test1_n v l1 v l2 v l3 16 17 18 19 20 21 22 25 24 23 47 48 49 50 45 46 73 72 71 70 69 68 75 74 y x 2.23mm 2.27mm 67 76
ml610q407/ml610q408/ml610q409 user's manual chapter 1 overview 1-9 1.3.1.5 pin layout of ml610q408 chip note: the assignment of the pads p30 to p35 are not in order. chip size: 2.27 mm 2.23 mm pad count: 88 pins minimum pad pitch: 80 m pad aperture: 70 m70 m chip thickness: 350 m voltage of the rear side of chip: v ss level. figure 1-6 dimensions of ml610q408 chip 64 65 66 29 28 27 26 v pp p53 p54 p55 p56 p57 p35 p33 p32 p34 88 p31 87 p30 86 p04 85 p03 84 p02 83 p01 82 p00 81 p24 80 p22 79 p21 78 p20 77 v ss seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 com4/seg2 com3/seg1 com2/seg0 com1 com0 c2 c1 p60 p61 p62 p63 seg35 seg34 seg33 seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 32 31 30 35 34 33 38 37 36 41 40 39 44 43 42 53 54 55 56 57 58 59 60 61 62 63 51 52 12 1 2 3 4 5 6 7 8 9 11 10 13 14 15 p52 p51 p50 p40 p41 p42 p43 p44 p45 p46 p47 v dd v ss v ddl xt0 xt1 reset_n test0 test1_n v l1 v l2 v l3 16 17 18 19 20 21 22 25 24 23 47 48 49 50 45 46 73 72 71 70 69 68 75 74 y x 2.23mm 2.27mm 67 76
ml610q407/ml610q408/ml610q409 user's manual chapter 1 overview 1-10 1.3.1.6 pin layout of ml610q409 chip note: the assignment of the pads p30 to p35 are not in order. chip size: 2.27 mm 2.23 mm pad count: 88 pins minimum pad pitch: 80 m pad aperture: 70 m70 m chip thickness: 350 m voltage of the rear side of chip: v ss level. figure 1-7 dimensions of ml610q409 chip 64 65 66 29 28 27 26 v pp p53 p54 p55 p56 p57 p35 p33 p32 p34 88 p31 87 p30 86 p04 85 p03 84 p02 83 p01 82 p00 81 p24 80 p22 79 p21 78 p20 77 v ss seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 com4/seg2 com3/seg1 com2/seg0 com1 com0 c2 c1 seg39 seg38 seg37 seg36 seg35 seg34 seg33 seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 32 31 30 35 34 33 38 37 36 41 40 39 44 43 42 53 54 55 56 57 58 59 60 61 62 63 51 52 12 1 2 3 4 5 6 7 8 9 11 10 13 14 15 p52 p51 p50 p40 p41 p42 p43 p44 p45 p46 p47 v dd v ss v ddl xt0 xt1 reset_n test0 test1_n v l1 v l2 v l3 16 17 18 19 20 21 22 25 24 23 47 48 49 50 45 46 73 72 71 70 69 68 75 74 y x 2.23mm 2.27mm 76 67
ml610q407/ml610q408/ml610q409 user's manual chapter 1 overview 1-11 1.3.1.7 pad coordinates of ml610q407/ml610q408/m610q409 chip table 1-1 pad coordinates of ml610q407/ml610q408/ml610q409 chip center: x=0,y=0 ml610q407/8/9 ml610q407/8/9 pad no. pad name x ( m) y ( m) pad no. pad name x ( m) y ( m) 1 p52 -853 -1009 49 seg22 535 1009 2 p51 -773 -1009 50 seg23 455 1009 3 p50 -693 -1009 51 seg24 375 1009 4 p40 -613 -1009 52 seg25 295 1009 5 p41 -533 -1009 53 seg26 215 1009 6 p42 -453 -1009 54 seg27 135 1009 7 p43 -373 -1009 55 seg28 55 1009 8 p44 -293 -1009 56 seg29 -25 1009 9 p45 -213 -1009 57 seg30 -105 1009 10 p46 -133 -1009 58 seg31 -185 1009 11 p47 -53 -1009 p67 (*1) 12 v dd 27 -1009 59 seg32 (*2)(*3) -295 1009 13 v ss 107 -1009 p66 (*1) 14 v ddl 187 -1009 60 seg33 (*2)(*3) -375 1009 15 xt0 267 -1009 p65 (*1) 16 xt1 427 -1009 61 seg34 (*2)(*3) -455 1009 17 reset_n 507 -1009 p64 (*1) 18 test0 587 -1009 62 seg35 (*2)(*3) -535 1009 19 test1_n 667 -1009 p63 (*1)(*2) 20 v l1 747 -1009 63 seg36 (*3) -615 1009 21 v l2 827 -1009 p62 (*1)(*2) 22 v l3 907 -1009 64 seg37 (*3) -695 1009 23 c0 1029 -840 p61 (*1)(*2) 24 c1 1029 -760 65 seg38 (*3) -775 1009 25 com0 1029 -680 p60 (*1)(*2) 26 com1 1029 -600 66 seg39 (*3) -855 1009 27 com2/seg0 1029 -520 67 v ss -1029 850 28 com3/seg1 1029 -440 68 p20 -1029 770 29 com4/seg2 1029 -360 69 p21 -1029 690 30 seg3 1029 -280 70 p22 -1029 610 31 seg4 1029 -200 71 p24 -1029 530 32 seg5 1029 -120 72 p00 -1029 430 33 seg6 1029 -40 73 p01 -1029 350 34 seg7 1029 40 74 p02 -1029 270 35 seg8 1029 120 75 p03 -1029 190 36 seg9 1029 200 76 p04 -1029 110 37 seg10 1029 280 77 p30 -1029 30 38 seg11 1029 360 78 p31 -1029 -50 39 seg12 1029 440 79 p34 -1029 -130 40 seg13 1029 520 80 p32 -1029 -210 41 seg14 1029 600 81 p33 -1029 -290 42 seg15 1029 680 82 p35 -1029 -370 43 seg16 1029 760 83 p57 -1029 -450 44 seg17 1029 840 84 p56 -1029 -530 45 seg18 855 1009 85 p55 -1029 -610 46 seg19 775 1009 86 p54 -1029 -690 47 seg20 695 1009 87 p53 -1029 -770 48 seg21 615 1009 88 v pp -1029 -850 (*1) pad for ml610q407 . (*2) pad for ml610q408. (*3) pad for ml610q409.
ml610q407/ml610q408/ml610q409 user's manual chapter 1 overview 1-12 1.3.2 list of pins primary function secondary func tion or tertiary function pin no. pad no. pin name i/o function secondary/ tertiary pin name i/o function 14,77 13,67 vss ? negative power supply pin ? ? ? ? 13 12 v dd ? positive power supply pin ? ? ? ? 15 14 v ddl ? power supply pin for internal logic (internally generated) ? ? ? ? 98 88 v pp ? power supply pin for flash rom ? ? ? ? 22 20 v l1 ? power supply pin for lcd bias (internally generated or connected to positive power supply pin) (*2) ? ? ? ? 23 21 v l2 ? power supply pin for lcd bias (internally generated or connected to positive power supply pin) (*2) ? ? ? ? 24 22 v l3 ? power supply pin for lcd bias (internally generated) ? ? ? ? 27 23 c1 ? capacitor connection pin for lcd bias generation ? ? ? ? 28 24 c2 ? capacitor connection pin for lcd bias generation ? ? ? ? 20 18 test0 i/o test pin ? ? ? ? 21 19 test1_n i test pin ? ? ? ? 19 17 reset_n i reset input pin ? ? ? ? 17 15 xt0 i low-speed clock oscillation pin ? ? ? ? 18 16 xt1 o low-speed clock oscillation pin ? ? ? ? 82 72 p00/exi0/ cap0 i input port, external interrupt, capture 0 input ? ? ? ? 83 73 p01/exi1/ cap1 i input port, external interrupt, capture 1 input ? ? ? ? 84 74 p02/exi2/ rxd0 i input port, external interrupt, uart0 received data ? ? ? ? 85 75 p03/exi3 i input port, external interrupt ? ? ? ? 86 76 p04/exi4/ t02p0ck i input port, timer 0/timer 2/pwm0 external clock input external interrupt ? ? ? ? 78 68 p20/led0 o output port secondary lsclk o low-speed clock output 79 69 p21/led1 o output port secondary outclk o high-speed clock output 80 70 p22/led2 o output port secondary md0 o melody 0 output 81 71 p24/led4 o output port secondary pwm0 o pwm0 output 87 77 p30 i/o input/output port secondary in0 i rc type adc0 oscillation input pin 88 78 p31 i/o input/output port secondary cs0 o rc type adc0 reference capacitor connection pin 89 79 p34 i/o input/output port secondary rct0 o rc type adc0 resistor/capacitor sensor connection pin 90 80 p32 i/o input/output port secondary rs0 o rc type adc0 reference resistor connection pin 91 81 p33 i/o input/output port secondary rt0 o rc type adc0 measurement resistor sensor connection pin 92 82 p35 i/o input/output port secondary rcm o rc type adc oscillation monitor
ml610q407/ml610q408/ml610q409 user's manual chapter 1 overview 1-13 primary function secondary function or tertiary function pin no. pad no. pin name i/o function secondary /tertiary pin name i/o function secondary ? ? ? 5 4 p40 i/o input/output port tertiary sin0 i ssio0 data input secondary ? ? ? 6 5 p41 i/o input/output port tertiary sck0 i/o ssio0 synchronous clock input/output secondary rxd0 i uart data input 7 6 p42 i/o input/output port tertiary sout0 o ssio0 data output secondary txd0 o uart data output 8 7 p43 i/o input/output port tertiary pwm0 o pwm0 output secondary in1 i rc type adc1 oscillation input pin 9 8 p44/ t02p0ck i/o input/output port, timer 0/timer 2/pwm0 external clock input tertiary sin0 i ssio0 data input secondary cs1 o rc type adc1 reference capacitor connection pin 10 9 p45/t13ck i/o input/output port, timer 1/timer 3 external clock input tertiary sck0 i/o ssio0 synchronous clock input/output secondary rs1 o rc type adc1 reference resistor connection pin 11 10 p46 i/o input/output port tertiary sout0 o ssio0 data output 12 11 p47 i/o input/output port secondary rt1 o rc type adc1 measurement resistor sensor connection pin secondary md0 o melody 0 output 4 3 p50/exi8 i/o input/output port, external interrupt tertiary sin1 i ssio1 data input secondary ? ? ? 3 2 p51/exi8 i/o input/output port, external interrupt tertiary sck1 i/o ssio1 synchronous clock input/output secondary ? ? ? 2 1 p52/exi8 i/o input/output port, external interrupt tertiary sout1 o ssio1 data output 97 87 p53/exi8 i/o input/output port, external interrupt ? ? ? ? secondary ? ? ? 96 86 p54/exi8 i/o input/output port, external interrupt tertiary sin1 i ssio1 data input secondary ? ? ? 95 85 p55/exi8 i/o input/output port, external interrupt tertiary sck1 i/o ssio1 synchronous clock input/output secondary ? ? ? 94 84 p56/exi8 i/o input/output port, external interrupt tertiary sout1 o ssio1 data output 93 83 p57/exi8 i/o input/output port, external interrupt ? ? ? ?
ml610q407/ml610q408/ml610q409 user's manual chapter 1 overview 1-14 primary function secondary function or tertiary function pin no. pad no. pin name i/o function secondary/ tertiary pin name i/o function 29 25 com0 o lcd common pin ? ? ? ? 30 26 com1 o lcd common pin ? ? ? ? 31 27 com2/ seg0 o lcd common/segment pin ? ? ? ? 32 28 com3/ seg1 o lcd common/segment pin ? ? ? ? 33 29 com4/ seg2 o lcd common/segment pin ? ? ? ? 34 30 seg3 o lcd segment pin ? ? ? ? 35 31 seg4 o lcd segment pin ? ? ? ? 36 32 seg5 o lcd segment pin ? ? ? ? 37 33 seg6 o lcd segment pin ? ? ? ? 38 34 seg7 o lcd segment pin ? ? ? ? 39 35 seg8 o lcd segment pin ? ? ? ? 40 36 seg9 o lcd segment pin ? ? ? ? 41 37 seg10 o lcd segment pin ? ? ? ? 42 38 seg11 o lcd segment pin ? ? ? ? 43 39 seg12 o lcd segment pin ? ? ? ? 44 40 seg13 o lcd segment pin ? ? ? ? 45 41 seg14 o lcd segment pin ? ? ? ? 46 42 seg15 o lcd segment pin ? ? ? ? 47 43 seg16 o lcd segment pin ? ? ? ? 48 44 seg17 o lcd segment pin ? ? ? ? 52 45 seg18 o lcd segment pin ? ? ? ? 53 46 seg19 o lcd segment pin ? ? ? ? 54 47 seg20 o lcd segment pin ? ? ? ? 55 48 seg21 o lcd segment pin ? ? ? ? 56 49 seg22 o lcd segment pin ? ? ? ? 57 50 seg23 o lcd segment pin ? ? ? ? 58 51 seg24 o lcd segment pin ? ? ? ? 59 52 seg25 o lcd segment pin ? ? ? ? 60 53 seg26 o lcd segment pin ? ? ? ? 61 54 seg27 o lcd segment pin ? ? ? ? 62 55 seg28 o lcd segment pin ? ? ? ? 63 56 seg29 o lcd segment pin ? ? ? ? 64 57 seg30 o lcd segment pin ? ? ? ? 65 58 seg31 o lcd segment pin ? ? ? ? p67 (*2) o output port ? ? ? ? 66 59 seg32 (*3) o lcd segment pin ? ? ? ? p66 (*2) o output port ? ? ? ? 67 60 seg33 (*3) o lcd segment pin ? ? ? ? p65 (*2) o output port ? ? ? ? 68 61 seg34 (*3) o lcd segment pin ? ? ? ? p64 (*2) o output port ? ? ? ? 69 62 seg35 (*3) o lcd segment pin ? ? ? ? p63 (*4) o output port ? ? ? ? 70 63 seg36 (*5) o lcd segment pin ? ? ? ? p62 (*4) o output port ? ? ? ? 71 64 seg37 (*5) o lcd segment pin ? ? ? ? p61 (*4) o output port ? ? ? ? 72 65 seg38 (*5) o lcd segment pin ? ? ? ? p60 (*4) o output port ? ? ? ? 73 66 seg39 (*5) o lcd segment pin ? ? ? ? (* 1 ) internally generated, or connect to either positive power supply pin (v dd ) or power supply pin for internal logic (v ddl ). for details, see "chapter 22 lcd drivers." (* 2 ) pin for ml610q407/ml610q408 (* 3 ) pin for ml610q409 (* 4 ) pin for ml610q407 (* 5 ) pin for ml610q408/ml610q409
ml610q407/ml610q408/ml610q409 user's manual chapter 1 overview 1-15 1.3.3 pin descriptions pin name i/o description primary/ secondary/ tertiary logic system reset_n i reset input pin. when this pin is set to a ?l? level, system reset mode is set and the internal section is initialized. when this pin is set to a ?h? level subsequently, pr ogram execution starts. a pull-up resistor is internally connected. ? negative xt0 i ? ? xt1 o crystal connection pin for low-speed clock. a 32.768 khz crystal resonator is c onnected to this pin. capacitors c dl and c gl are connected across this pin and v ss . (see appendix c measuring circuit 1) ? ? lsclk o low-speed clock output. assigned to the secondary function of the p20 pin. secondary ? outclk o high-speed clock output pin. this pin is used as the secondary function of the p21 pin. secondary ? general-purpose input port p00 to p04 i general-purpose input port. primary positive general-purpose output port p20 to p22, p24 o general-purpose output port. this cannot be used as the general output port when used as the secondary function. primary positive general-purpose input/output port p30 to p35 i/o general-purpose input/output port. this cannot be used as the general input/output port when used as the secondary function. primary positive p40 to p47 i/o general-purpose input/output port. this cannot be used as the general input/output port when used as the secondary or tertiary function. primary positive p50 to p57 o general-purpose output port. this cannot be used as the general output port when used as the secondary function. primary positive p60 to p63 i/o general-purpose input/output port. incorporated only into ml610q 407/8, and not into ml610q409. primary positive p64 to p67 i/o general-purpose input/output port. incorporated only into ml610q 407, and not into ml610q408/ ml610q409. primary positive
ml610q407/ml610q408/ml610q409 user's manual chapter 1 overview 1-16 pin name i/o description primary/ secondary/ tertiary logic uart txd0 o uart data output pin. this pi n is used as the secondary function of the p43 pin. secondary positive rxd0 i uart data input pin. this pi n is used as the secondary function of the p42 or the primary f unction of the p02 pin. primary/ secondary positive synchronous serial (ssio) sck0 i/o synchronous serial clock input/ output pin. this pin is used as the tertiary function of the p41 or p45 pin. tertiary ? sin0 i synchronous serial data input pin. this pin is used as the tertiary function of the p40 or p44 pin. tertiary positive sout0 o synchronous serial data output pin. this pin is used as the tertiary function of the p42 or p46 pin. tertiary positive sck1 i/o synchronous serial clock input/ output pin. assigned to the tertiary function of the p 51 pin and p54 pin. tertiary ? sin1 i synchronous serial data input pi n. assigned to the tertiary function of the p50 pin and p54 pin. tertiary positive sout1 o synchronous serial data output pin. assigned to the tertiary function of the p52 pin and p56 pin. tertiary positive pwm pwm0 o pwm0 output pin. this pin is used as the secondary function of the p24 and tertiary function of the p43 pin. secondary tertiary positive t0p02ck o pwm0 external clock input pi n. this pin is used as the primary function of the p 04 pin and p44 pin. primary ? external interrupt exi0-4 i external maskable interrupt input pins. interrupt enable and edge selection can be performed for each bit by software. these pins are used as the primary functions of the p00 to p04 pins. primary positive/ negative exi8 i external maskable interrupt input pins. interrupt enable and edge selection can be performed for each bit by software. assigned to the primary function of the p50 to p57 pins. primary positive/ negative capture cap0 i primary positive/ negative cap1 i capture trigger input pins. the va lue of the time base counter is captured in the register sync hronously with the interrupt edge selected by software. these pins are used as the primary functions of the p00 pin(cap0) and p01 pin(cap1). primary positive/ negative timer t0p02ck i external clock input pin used for both timer 0 and timer 2. this pin is used as the primary functi on of the p04 pin and p44 pin. primary ? t13ck i external clock input pin used for both timer 1 and timer 3. this pin is used as the primary f unction of the p45 pin. primary ? melody md0 o melody/buzzer signal output pin. this pin is used as the secondary function of the p22 and p50 pins. secondary positive/ negative led drive led0 to led2, led4 o n-channel open drain output pins to drive led. this pin is used as the primary function of t he p20 to p22 and p24 pins. primary positive /negative
ml610q407/ml610q408/ml610q409 user's manual chapter 1 overview 1-17 pin name i/o description primary/ secondary/ tertiary logic rc oscillation type a/d converter in0 i channel 0 oscillation input pin. this pin is used as the secondary function of the p30 pin. secondary ? cs0 o channel 0 reference capacitor c onnection pin. this pin is used as the secondary function of the p31 pin. secondary ? rs0 o this pin is used as the secondar y function of the p32 pin which is the reference resistor c onnection pin of channel 0. secondary ? rct0 o resistor/capacitor sensor connection pin of channel 0 for measurement. this pin is used as the secondary function of the p34 pin. secondary ? rt0 o resistor sensor connection pin of channel 0 for measurement. this pin is used as the secondary function of the p33 pin. secondary ? rcm o rc oscillation monitor pin. this pin is used as the secondary function of the p35 pin. secondary ? in1 i oscillation input pin of channel 1. this pin is used as the secondary function of the p44 pin. secondary ? cs1 o reference capacitor connection pi n of channel 1. this pin is used as the secondary functi on of the p45 pin. secondary ? rs1 o reference resistor connection pin of channel 1. this pin is used as the secondary function of the p46 pin. secondary ? rt1 o resistor sensor connection pin for measurement of channel 1. this pin is used as the secondary function of the p47 pin. secondary ? lcd drive signal com0 to com4 o common output pins. com2, com3, and com4 can be switched to seg0, seg1, and seg2, respec tively, through the register setting. to change the setting, sw itch between com4 and seg2 for one pin and switch between com3 , com4 and seg1, seg2 for two pins. ? ? seg0 to seg23 o segment output pin. the seg0, seg1, and seg2 pins are for switching the register setting with the com2, com3, and com4. ? ? seg24 to seg27 o segment output pin. incor porated into m l610q408/ml610q409, not into ml610q407. ? ? seg28 to seg31 o segment output pin. incorpor ated into ml610q409, not into ml610q407/ml610q408. lcd driver power supply v l1 ? ? ? v l2 ? ? ? v l3 ? power supply pin for lcd bias (internally generated) or power supply connection pin. depending on lcd bias setting and v dd voltage level, v dd or v ddl or capacitor is connected. for details of the connection method, see c hapter 22, "lcd drivers". ? ? c1 ? ? ? c2 ? power supply pins for lcd bias (internally generated). capacitor c 12 (see appendix c measuring circui t 1) is connected between c1 and c2. ? ?
ml610q407/ml610q408/ml610q409 user's manual chapter 1 overview 1-18 pin name i/o description primary/ secondary/ tertiary logic test test0 i/o pin for testing. a pull-down resist or is internally connected. ? positive test1_n i pin for testing. a pull-up resist or is internally connected. ? negative power supply v ss ? negative power supply pin. ? ? v dd ? positive power supply pin. ? ? v ddl ? positive power supply pin (internally generated) for internal logic. capacitors c l0 and c l1 (see appendix c measuring circuit 1) are connected between this pin and v ss . ? ? v pp ? power supply pin for programming flash rom. a pull-down resistor is internally connected. ? ?
ml610q407/ml610q408/ml610q409 user's manual chapter 1 overview 1-19 1.3.4 handling of unused pins table 1-2 shows methods of terminating the unused pins. table 1-2 termination of unused pins pin recommended pin handling v pp open v l1 open v l2 open v l3 open c1, c2 open reset_n open test0 open test1_n open p00 to p04 v dd or v ss p20 to p22, p24 open p30 to p35 open p40 to p47 open p50 to p57 open p60 to p67 open com0 to com 4 open seg0 to seg 39 open note: it is recommended to set the unused input ports and input/output ports to the inputs with pull-down resistors/pull-up resistors or the output mode since the supply current may become excessively large if the pins are left open in the high impedance input setting.
chapter 2 cpu and memory space
ml610q407/ml610q408/ml610q409 user's manual chapter 2 cpu and memory space 2-1 2. cpu and memory space 2.1 overview this lsi includes 8-bit cpu nx-u8/100 and the memory model is small model. for details of the cpu nx-u8/100, see ?nx-u8/100 core instruction manual?. 2.2 program memory space the program memory space is used to store program c odes, table data (rom wi ndow), or vector tables. the program codes have a length of 16 bits and are specified by a 16-bit program counter (pc). the rom window area data has a length of 8 bits and can be used as table data. the vector table, which has 16-bit long data, can be used as reset vectors, hardware interrupt vectors, and software interrupt vectors. the program memory space consists of one segment and has 16-kbyte (8-kword) capacity. figure 2-1 shows the configuration of the program memory space. pc 0000h 00ffh vector table area or program code rom window area 0100h program code area or rom window area 3c00h 3fffh test data area 8bit figure 2-1 configuration of program memory space note: ~ the 1024 bytes (512 words) from 3c00h to 3fffh are the test data area. ~ the test data area is rewritable but cannot be used as the program code area. ~ in case mask rom version emulation function is not used, write "0ffh" to the test data area. if data in the area is uncertain o r other data (i.e. not 0ffh), operating with the code cannot be guaranteed. ~ in case mask rom version emulation functi on is used, see chapter 25, "mask rom ve rsion emulation function" for the write data to the test data area. ~ set ?0ffh? data (brk instruction) in th e unused area of the program memory space.
ml610q407/ml610q408/ml610q409 user's manual chapter 2 cpu 2-2 2.3 data memory space the data memory space of this lsi consists of the rom window area, 1kbyte ram area, and sfr area of segment 0. the data memory has the 8-bit length and is specified by the addressing specifi ed by each instruction. figure 2-2 shows the configurati on of the data memory space. dsr: data address segment 0 0000h rom window area 3fffh 4000h dfffh unused area e000h e3ffh ram area 1k byte e400h efffh unused area f000h ffffh sfr area 8bit figure 2-2 configuration of data memory space note: ~ the contents of the ram area are undefined at sy stem reset. initialize this area by software.
ml610q407/ml610q408/ml610q409 user's manual chapter 2 cpu and memory space 2-3 2.4 instruction length the length of an instruction is 16 bits. 2.5 data type the data types supported include byte (8 bits) and word (16 bits).
ml610q407/ml610q408/ml610q409 user's manual chapter 2 cpu 2-4 2.6 description of registers 2.6.1 list of registers address name symbol (byte) symbol (word) r/w size initial value 0f000h data segment register dsr ? r/w 8 00h
ml610q407/ml610q408/ml610q409 user's manual chapter 2 cpu and memory space 2-5 2.6.2 data segment register (dsr) address: 0f000h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 dsr ? ? ? ? dsr3 dsr2 dsr1 dsr0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 dsr is a special function register (sfr) to retain a data segment. always use this register with the in itial state (0). for details of dsr, s ee ?nx-u8/100 core instruction manual?. [description of bits] ? dsr3-dsr0 (bits 3 to 0) dsr3 dsr2 dsr1 dsr0 description 0 0 0 0 initial value in other than above prohibited
chapter 3 reset function
ml610q407/ml610q408/ml610q409 user's manual chapter 3 reset function 3-1 3. reset function 3.1 overview this lsi has the five reset functions shown below. if any of the five reset conditions is satisfied, this lsi enters system reset mode. ? reset by the reset_n pin ? reset by power-on detection ? reset by the low-speed oscillation stop detection ? reset by the 2 nd watchdog timer (wdt) overflow ? software reset by execution of the brk instruction 3.1.1 features ? the reset_n pin has an internal pull-up resistor ? the low-speed oscillation stop detection time is 19 ms (typ.) ? 250 ms, 1 sec, 4 sec, or 16 sec can be selected as the watchdog timer (wdt) overflow period ? built-in reset status register (rstat) indicating the reset generation causes ? only the cpu is reset by the brk instruction (neither the ram area nor the sfr area are reset). 3.1.2 configuration figure 3-1 shows the configuration of the reset generation circuit. rstat : reset status register figure 3-1 configuration of reset generation circuit 3.1.3 list of pins pin name input/output function reset_n i reset input pin power on reset low-speed oscillation reset when stop of the low-speed clock is detected reset_n reset v dd wdt reset rstat data bus
ml610q407/ml610q408/ml610q409 user's manual chapter 3 reset function 3-2 3.2 description of registers 3.2.1 list of registers address name symbol (byte) symbol (word) r/w size initial value 0f001h reset status register rstat ? r/w 8 ? 3.2.2 reset status register (rstat) address: 0f001h access: r/w access size: 8-bit initial value: undefined 7 6 5 4 3 2 1 0 rstat ? ? ? ? ? wdtr xstr por r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 x 1 rstat is a special function register (sfr) that indicates the causes by which the reset is generated. at the occurrence of reset, the contents of rstat are not initialized, while the bit indicating the cause of the reset is set to ?1?. when checking the reset cause using this function, perform write operation to rstat in advance and initialize the contents of rstat to ?00h?. [description of bits] ? por (bit 0) the por bit is a flag that indicates that the power-on reset is generated. this bit is set to ?1? when powered on. por description 0 power-on reset not generated 1 power-on reset generated ? xstr (bit 1) the xstr bit is a flag that indicates the generation of low-speed oscillation stop detect reset. when low-speed oscillation stops for the period specified by the low-speed oscillation stop detection time (t stop ) or more, this bit is set to ?1?. xstr description 0 low-speed oscillation stop detect reset not occurred 1 low-speed oscillation stop detect reset occurred ? wdtr (bit 2) the wsdtr is a flag that indicates that the watchdog timer reset is generated. this bit is set to ?1? when the reset by overflow of the watchdog timer is generated. wdtr description 0 watchdog timer reset not occurred 1 watchdog timer reset occurred note: no flag is provided that indicates the occurrence of reset by the reset_n pin.
ml610q407/ml610q408/ml610q409 user's manual chapter 3 reset function 3-3 3.3 description of operation 3.3.1 operation of system reset mode system reset has the highest priority among all the processi ngs and any other processing being executed up to then is cancelled. the system reset mode is set by any of the following causes. ? reset by the reset_n pin ? reset by power-on detection ? reset by the low-speed oscillation stop detection ? reset by watchdog timer (wdt) overflow ? software reset by the brk instruction (only the cpu is reset) in system reset mode, the following processing is performed. the power circuit is initialized. however, it is not initialized by the reset by the brk instruction execution. for the details of the power circuit, refer to chapter 23, ?power circuit?. all the special function registers ( sfrs) whose initial value is not unde fined are initialized. however, the initialization is not performed by software reset due to execution of the brk instruction. see appendix a ?registers? for the initial values of the sfrs. cpu is initialized. ? all the registers in cpu are initialized. ? the contents of addresses 0000h and 0001h in the program memory are set to the stack pointer (sp). ? the contents of addresses 0002h and 0003h in the program memory are set to the program counter (pc). however, when the interrupt level ( eleevl) of the program status word ( psw) at reset by the brk instruction is 1 or lower, the contents of addresses 0004h and 0005h of the program memory are set in the program counter (pc). for the brk instruction, see ?nx-u8/100 core instruction manual?. note: in system reset mode, the contents of data memory a nd those of any sfr whose initial value is undefined are not initialized and are undefined. initialize them by software. in system reset mode by the brk instruction, no special function register (sfr) that has a fixed initial value is initialized either. therefore initialize such an sfr by software.
chapter 4 mcu control function
ml610q407/ml610q408/ml610q409 user's manual chapter 4 mcu control function 4-1 4. mcu control function 4.1 overview the operating states of this lsi are classified into the following 4 modes including system reset mode: (1) system reset mode (2) program run mode (3) halt mode (4) stop mode for system reset mode, see ch apter 3, ?reset function?. 4.1.1 features ? halt mode, where the cpu stops operating and only the peripheral circuit is operating ? stop mode, where both low-speed oscillation and high-speed oscillation stop ? stop code acceptor function, which controls transition to stop mode ? block control function, which power downs the circu its of unused peripherals (reset registers and stop clock supplies) 4.1.2 configuration figure 4-1 shows an operating state transition diagram. figure 4-1 operating state transition diagram system reset mode reset or brk instruction release reset program operation mode halt mode stop mode reset reset stp=?1? external interrupt hlt=?1? interrupt power on
ml610q40/7/ml610q408/ml610q409 user's manual chapter 4 mcu control function 4-2 4.2 description of registers 4.2.1 list of registers address name symbol (byte) symbol (word) r/w size initial value 0f008h stop code acceptor stpacp ? w 8 ? 0f009h standby control register sbycon ? w 8 00h 0f028h block control register 0 blkcon0 ? r/w 8 00h 0f029h block control register 1 blkcon1 ? r/w 8 00h 0f02ah block control register 2 blkcon2 ? r/w 8 00h 0f02bh block control register 3 blkcon3 ? r/w 8 00h 0f02ch block control register 4 blkcon4 ? r/w 8 00h
ml610q407/ml610q408/ml610q409 user's manual chapter 4 mcu control function 4-3 4.2.2 stop code acceptor (stpacp) address: 0f008h access: w access size: 8-bit initial value:?(undefined) 7 6 5 4 3 2 1 0 stpacp ? ? ? ? ? ? ? ? w w w w w w w w w initial value - - - - - - - - stpacp is a write-only special function register (sfr) that is used for setting a stop mode. when stpacp is read, ?00h? is read. when data is written to stpacp in the order of ?5nh?(n: an arbitrary value) and ?0anh?(n : an arbitrary value), the stop code acceptor is enabled. when the stp b it of the standby control register (sbyc on) is set to ?1? in this state, the mode is changed to the stop mode. when the stop mode is set, the stop code acceptor is disabled. when another instruction is executed between the instruction that writes ?5nh? to stpacp and the instruction that writes ?0anh?, the stop code acceptor is enab led after ?0anh? is written. however, if data other than ?0anh? is written to stpacp after ?5nh? is written, the ?5nh? write processing becomes invalid so that data must be written again starting from ?5nh?. during a system reset, the st op code acceptor is disabled. note: the stop code acceptor cannot be enabled on the conditi on of that both any interrupt enable flag and the corresponding interrupt request flag are ?1?(an interrupt request occurre nce with resetting mie flag will have the condition).
ml610q40/7/ml610q408/ml610q409 user's manual chapter 4 mcu control function 4-4 4.2.3 standby control register (sbycon) address: 0f009h access: w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 sbycon ? ? ? ? ? ? stp hlt w w w w w w w w w initial value 0 0 0 0 0 0 0 0 sbycon is a special function register (sfr) to control operating mode of mcu. [description of bits] ? stp (bit 1) the stp bit is used for setting the stop mode. when the stp bit is set to ?1? with the stop code adapter enabled by using stpacp, the mode is changed to the stop mode. when any of the p00 to p04 interrupt requests enabled by the interrupt enable register 1 (ie1) o ccurs or an external 8 inte rrupt request enabled by the interrupt enable register 2 (ie2) occurs, the stp becomes "0" and the operation returns to the program run mode. ? hlt (bit 0) the halt bit is used for setting a halt mode. when the halt bit is set to ?1?, the mode is changed to the halt mode. when the wdt interrupt request or enabled (the interrupt enable flag is ?1?) interrupt request is issued, the halt bit is set to ?1? and the mode is returned to program run mode. stp hlt description 0 0 program run mode (initial value) 0 1 halt mode 1 0 stop mode 1 1 prohibited note: the mode cannot be changed to halt mode or stop mode on the condition of that both any interrupt enable flag and the corresponding interrupt request flag are ?1?(an interrupt request occurrence with resetting mie flag will have the condition). when a maskable interrupt source (interr upt with enable bit) occurs while the mie flag of the program status word (psw) in the nx-u8/100 core is ?0?, the stop mode and the halt mode are simply released and interrupt processing is not performed. for details of psw, see ?nx-u8/100 core instruction manual?.
ml610q407/ml610q408/ml610q409 user's manual chapter 4 mcu control function 4-5 4.2.4 block control register 0 (blkcon0) address: 0f028h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 blkcon0 ? ? ? ? dtm3 dtm2 dtm1 dtm0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 blkcon0 is a special function register (sfr) to control each block operation. [description of bits] ? dtm0 (bit 0) the dtm0 bit is used to control timer 0 operation. dtm0 description 0 enable operating timer 0 (initial value) 1 disable operating timer 0 ? dtm1 (bit 1) the dtm1 bit is used to control timer 1 operation. dtm1 description 0 enable operating timer 1 (initial value) 1 disable operating timer 1 ? dtm2 (bit 2) the dtm2 bit is used to control timer 2 operation. dtm2 description 0 enable operating timer 2 (initial value) 1 disable operating timer 2 ? dtm3 (bit 3) the dtm3 bit is used to control timer 3 operation. dtm3 description 0 enable operating timer 3 (initial value) 1 disable operating timer 3 note: ?when any flag is set to "1" (disable operation), the function of the applicable block is reset (all registers are initialized) and the clock supply to such bl ock stops. when this flag is set to "1 ", the writing to all registers in the applicable block becomes invalid, and thus the reading from such register becomes the initial value. when using the function of the applicable block, ensure to reset the appli cable flag of this block control register to "0" (enable operation). ?see chapter 9, ?timers? for detail about operation of timer 0, timer 1, timer 2 and timer 3.
ml610q40/7/ml610q408/ml610q409 user's manual chapter 4 mcu control function 4-6 4.2.5 block control register 1 (blkcon1) address: 0f029h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 blkcon1 ? dcapr ? ? ? ? ? dpw0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 blkcon1 is a special function register (sfr) to control each block operation. [description of bits] ? dpw0 (bit 0) the dpw0 bit is used to control pwm0 operation. dpw0 description 0 enable operating pwm0 (initial value) 1 disable operating pwm0 ? dcapr (bit 6) the dcapr bit is used to control capture operation. dcapr description 0 enable operating capture (initial value) 1 disable operating capture note: ?when any flag is set to "1" (disable operation), the function of the applicable block is reset (all registers are initialized) and the clock supply to such bl ock stops. when this flag is set to "1 ", the writing to all registers in the applicable block becomes invalid, and thus the reading from such register becomes the initial value. when using the function of the applicable block, ensure to reset the appli cable flag of this block control register to "0" (enable operation). ?see chapter 8, ?capture? for detail about operation of capture. ?see chapter 10, ?pwm? for detail about operation of pwm.
ml610q407/ml610q408/ml610q409 user's manual chapter 4 mcu control function 4-7 4.2.6 block control register 2 (blkcon2) address: 0f02ah access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 blkcon2 ? ? ? ? ? dua0 dsio1 dsio0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 blkcon2 is a special function register (sfr) to control each block operation. [description of bits] ? dsio0 (bit 0) the dsio0 bit is used to control the synchronous serial port o operation. dsio0 description 0 enable operating synchronous serial port 0 (initial value) 1 disable operating synchronous serial port 0 ? dsio1 (bit 1) the dsio1 bit is used to control the synchronous serial port o operation. dsio1 description 0 enable operating synchronous serial port 1 (initial value) 1 disable operating synchronous serial port 1 ? dua0 (bit 2) the dua0 bit is used to control uart operation. dua0 description 0 enable operating uart (initial value) 1 disable operating uart note: ?when any flag is set to "1" (disable operation), the function of the applicable block is reset (all registers are initialized) and the clock supply to such bl ock stops. when this flag is set to "1 ", the writing to all registers in the applicable block becomes invalid, and thus the reading from such register becomes the initial value. when using the function of the applicable block, ensure to reset the appli cable flag of this block control register to "0" (enable operation). ?see chapter 13, ?uart? for detail about operation of uart. ?see chapter 12, ?synchronous serial port? for detail about operation of ssio.
ml610q40/7/ml610q408/ml610q409 user's manual chapter 4 mcu control function 4-8 4.2.7 block control register 3 (blkcon3) address: 0f02bh access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 blkcon3 ? ? ? ? ? ? ? dmd0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 blkcon3 is a special function register (sfr) to control each block operation. [description of bits] ? dmd0 (bit 0) the dmd0 bit is used to control the melody driver 0 operation. dmd0 description 0 enable operating melody/buzzer (initial value) 1 disable operating melody/buzzer note: ?when any flag is set to "1" (disable operation), the function of the applicable block is reset (all registers are initialized) and the clock supply to such bl ock stops. when this flag is set to "1 ", the writing to all registers in the applicable block becomes invalid, and thus the reading from such register becomes the initial value. when using the function of the applicable block, ensure to reset the appli cable flag of this block control register to "0" (enable operation). ?see chapter 20, ?melody driver? for de tail about operation of melody/buzzer.
ml610q407/ml610q408/ml610q409 user's manual chapter 4 mcu control function 4-9 4.2.8 block control register 4 (blkcon4) address: 0f02ch access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 blkcon4 ? dlcd ? ? ? ? drad ? r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 blkcon4 is a special function register (sfr) to control each block operation. [description of bits] ? drad (bit 1) the drad bit is used to control the rc oscillation type a/d converter operation. drad description 0 enable operating rc oscillation type a/d converter (initial value) 1 disable operating rc oscillation type a/d converter ? dlcd (bit 6) the dlcd bit is used to control lcd driver operation. dlcd description 0 enable operating lcd driver (initial value) 1 disable operating lcd driver note: ?when any flag is set to "1" (disable operation), the function of the applicable block is reset (all registers are initialized) and the clock supply to such bl ock stops. when this flag is set to "1 ", the writing to all registers in the applicable block becomes invalid, and thus the reading from such register becomes the initial value. when using the function of the applicable block, ensure to reset the appli cable flag of this block control register to "0" (enable operation). ?see chapter 22, ?lcd driver? for detail about operation of lcd driver. ?see chapter 21, ?rc oscillation type a/d converter? for detail about operation of rc oscillation type a/d converter.
ml610q40/7/ml610q408/ml610q409 user's manual chapter 4 mcu control function 4-10 4.3 description of operation 4.3.1 program run mode the program run mode is the state where the cpu executes instructions sequentially. at power-on reset, low-speed oscillation stop detect rese t, wdt overflow reset, or reset_n pin reset, the cpu executes instructions from the addresses that are set in addresses 0002h and 0003h of program memory (rom) after the system reset mode is released. at reset by the brk instruction, the cpu executes instructions from the addresses that are set in the addresses 0004h and 0005h of the program memory after the system reset mode is released. however, when the value of the interrupt level bit (elevel) of the program status word (psw) is 02h or higher at execution of th e brk instruction (after the occurrence of the wdt interrupt), the cpu executes instructi ons from the addresses that are set in the addresses 0002h and 0003h. for details of the brk instruction and psw, see the ?nx-u8 /100 core instruction manual? and for the reset function, see chapter 3, ?reset function?. 4.3.2 halt mode the halt mode is the state where the cpu interrupts execution of instructions and only the peripheral circuits are running. when the hlt bit of the standby control register (sbycon) is set to ?1?, the halt mode is set. when a wdt interrupt request, or an interrupt request enabled by an interrupt enable register (ie1?ie7) is issued, the hlt bit is set to ?0? on the falling edge of the next system clock (sysclk) and the halt mode is returned to the program run mode released. figure 4-2 shows the operation waveforms in halt mode. cpucl k ??? sysclk ??` ha lt ` z? ??` sbycon. hl t figure 4-2 operation waveforms in halt mode note: since up to two instructions are executed during the period between halt mode release and a transition to interrupt processing, place two nop instructi ons next to the instruction th at sets the hlt bit to ?1?. system clock interrupt request program run mode halt m ode program run mode
ml610q407/ml610q408/ml610q409 user's manual chapter 4 mcu control function 4-11 4.3.3 stop mode the stop mode is the state where low-speed oscillation and high-speed oscillation stop and the cpu and peripheral circuits stop the operation. when the stop code acceptor is enabled by writing ?5nh?(n: an arbitrary value) and ?0anh?(n: an arbitr ary value) to the stop code acceptor (stpacp) sequentially and the stp bit of th e standby control register (s bycon) is set to ?1?, the stop mode is entered. when the stop mode is set, the stop code acceptor is disabled. when any of the p00 to p04 interrupt requests or an external 8 interrupt request occurs with the interrupt enabled (the interrupt enable flag is "1"), the stp bit is set to "0", the stop mode is released, and the mode is returned to the program run mode. 4.3.3.1 stop mode when cpu operates with low-speed clock when the stop code acceptor is in the enab led state and the stp bit of sbycon is set to ?1?, the stop mode is entered, stopping low-speed oscillation and high-speed oscillation. when any of the p00 to p04 interrupt request or an external 8 interrupt request occurs with the interrupt enabled (interrupt enabled flag is "1") state, the stp bit becomes "0" and the low-speed oscillation resumes. if the high-speed clock was oscillating before the stop mode is entered, the high-speed oscillation restarts. when the high-speed clock was not oscillating before the stop mode is entered, high-speed oscillation does not start. when an interrupt request occurs, the stop mode is released after the elapse of the low-speed oscillation start time (t xtl ) and the low-speed clock (lsclk) osc illation stabilization time (8192-pulse count ), the mode is returned to the program run mode, and the low-speed clock (lsclk) restarts supply to the peripheral circuits. if the high-speed clock already started oscillation at this time, the high-speed clocks (osclk and hsclk) also restart supply to the peripheral circuits. for the low-speed oscillation start time (t xtl ), see appendix c, ?electrical characteristics?. figure 4-3 shows the operation waveforms in stop m ode when cpu operates with the low-speed clock. figure 4-3 operation waveforms in stop mode when cpu operates with low-speed clock low-speed oscillation waveform oscillation waveform sysclk oscillation waveform oscillation waveform high-speed oscillation waveform sbycon.stp bit lsclk hsclk hsclk waveform hsclk program run mode stop mode pro g ram run mode interrupt request t xtl low-speed oscillation 8192 counts high-speed oscillation 16 counts hiz high-speed oscillation maximum 1 count
ml610q40/7/ml610q408/ml610q409 user's manual chapter 4 mcu control function 4-12 4.3.3.2 stop mode when cpu operates with high-speed clock when the cpu is operating with the high-speed clock and the stp bit of sbycon is set to ?1? with the stop code acceptor enabled, the stop mode is entered and hi gh-speed oscillation and low-speed oscillation stop. when any of the p00 to p04 interrupt request or an external 8 interrupt request occurs with the interrupt enabled (interrupt enabled flag is "1") state, the stp bit becomes "0" and the high-speed and low-speed oscillation resumes. when an interrupt request is issued, the stop mode is released after the elapse of the high-speed oscillation start time (t rc ) and the high-speed clock (osclk) osc illation stabilization time (16-pulse count ), the mode is returned to the program run mode, and the high-speed clocks (osclk a nd hsclk) restart supply to the peripheral circuits. the low-speed clock (lsclk) restarts suppl y to the peripheral circuits after the el apse of the low-speed oscillation start time (t xtl ) and low-speed clock (lsclk) osc illation stabilization time (8192 count). for the high-speed oscillation start time (t xth ) and low-speed oscillation start time (t xtl ), see the ?electrical characteristics? section in appendix c. figure 4-4 shows the operation waveforms in stop m ode when cpu operates with the high-speed clock. figure 4-4 operation waveforms in stop mode when cpu operates with high-speed clock note: since up to two instructions are executed during the period between stop mode release and a transition to interrupt processing, place two nop instructi ons next to the instruction th at sets the stp bit to ?1?. low-speed oscillation waveform low-speed high-speed oscillation waveform high-speed oscillation waveform high-speed oscillation waveform sbycon.stp bit lsclk osclk waveform osclk waveform osclk program run mode stop mode program run mode interrupt request t xtl high-speed oscillation 16 counts sysclk,hsclk waveform t rc sysclk,hsclk 8192 counts sysclk, hsclk hiz l ow - spee d oscillation maximum 1 count
ml610q407/ml610q408/ml610q409 user's manual chapter 4 mcu control function 4-13 4.3.4 note on return operation from stop/halt mode the operation of returning from the stop mode and halt m ode varies according to the interrupt level (elevel) of the program status word (psw), master in terrupt enable flag (mie), the contents of the interrupt enable register (ie0 to ie3), and whether the interrupt is a non-maskable interrupt or a maskable interrupt. for details of psw and the ie and irq registers, see ?nx-u8 /100 core instruction manual? and chapter 5, ?interrupt?, respectively. table 4-1 and table 4-2 show the re turn operations from stop/halt mode. table 4-1 return operation from stop/halt mode (non-maskable interrupt) elevel mie ien.m irqn.m return operation from stop/halt mode * * ? 0 not returned from stop/halt mode. 3 * ? 1 after the mode is returned from stop/halt mode, the program operation restarts from the instruct ion following the instruction that sets the stp/hlt bit to ?1?. the program operation does not go to the interrupt routine. 0,1,2 * ? 1 after the mode is returned from the stop/halt mode, program operation restarts from the instruct ion following the instruction that sets the stp/hlt bit to ?1?, t hen goes to the interrupt routine. table 4-2 return operation from stop/halt mode (maskable interrupt) elevel mie ien.m irqn.m return operation from stop/halt mode * * * 0 * * 0 1 not returned from stop/halt mode. * 0 1 1 2,3 1 1 1 after the mode is returned from stop/halt mode, the program operation restarts from the instruct ion following the instruction that sets the stp/hlt bit to ?1?. the program operation does not go to the interrupt routine. 0,1 1 1 1 after the mode is returned from the stop/halt mode, program operation restarts from the instruct ion following the instruction that sets the stp/hlt bit to ?1?, t hen goes to the interrupt routine. note: ?if the elevel bit is 0h, it indicates that the cpu is performing neither non-maskable interrupt processing nor maskable interrupt processing nor software interrupt processing. ?if the elevel bit is 1h, it indicates that the cpu is perform ing maskable interrupt proce ssing or software interrupt processing. (elevel is set duri ng interrupt transition cycle.) ?if the elevel bit is 2h, it indicates that the cpu is pe rforming non-maskable interrupt processing. (elevel is set during interrupt transition cycle.) ?if the elevel bit is 3h, it indicates that the cpu is perfo rming interrupt processing speci fic to the emulator. this setting is not allowed in normal applications.
ml610q40/7/ml610q408/ml610q409 user's manual chapter 4 mcu control function 4-14 4.3.5 block control function this lsi has a block control function, which resets and comp letely turns operating circuits of unused peripherals off to make even more reducing current consumption. for each block control register, the initial value of each flag is "0", meaning the operation of each block is enabled. when any flag is set to "1" (disable operating), the function of the applicable block is reset and the clock supply to this block is stopped. when this flag is set to "1", the writing to all registers in the appli cable block becomes invalid, and thus the reading from such register becomes the initial value. when using the function of the applicable block, ensure to reset the applicable flag of this block control register to "0" (enable operation). ? blkcon0 register: controls (enables/disables) the operation of the timers 0, 1, 2, and 3 circuits. ? blkcon1 register: controls (enables/disables) the operation of the pwm0 and capture circuits. ? blkcon2 register: controls (enables/disables) the operation of the uart0, ssio0, and ssio1 circuits. ? blkcon3 register: controls (disables/enables) the operation of the melody driver 0 circuit. ? blkcon4 register: controls (disables/enables) the operation of the lcd driver and rc oscillation type a/d converter circuits.
chapter 5 interrupt
ml610q407/ml610q408/ml610q409 user's manual chapter 5 interrupt 5-1 5. interrupts 5.1 overview this lsi has 21 interrupt sources (external interrupts: 6 sour ces, internal interrupts: 15 sources) and a software interrupt (swi). for details of each interrupt , see the following chapters: chapter 7, ?time base counter? chapter 9, ?timer? chapter 10, ?pwm? chapter 11, ?watchdog timer? chapter 12, ?synchronous serial port? chapter 13, ?uart? chapter 14, ?port 0? chapter 18, ?port 5? chapter 20, ?melody driver? chapter 21, ?rc oscillati on type a/d converter? 5.1.1 features ? non-maskable interrupt source: 1 (internal sources: 1) ? maskable interrupt sources: 27 (internal sources: 14, external sources: 13) ? software interrupt (swi): maximum 64 sources ? external interrupts allow edge selection and sampling selection
ml610q407/ml610q408/ml610q409 user's manual chapter 5 interrupt 5-2 5.2 description of registers 5.2.1 list of registers address name symbol (byte) symbol (word) r/w size initial value 0f011h interrupt enable register 1 ie1 ? r/w 8 00h 0f012h interrupt enable register 2 ie2 ? r/w 8 00h 0f013h interrupt enable register 3 ie3 ? r/w 8 00h 0f014h interrupt enable register 4 ie4 ? r/w 8 00h 0f015h interrupt enable register 5 ie5 ? r/w 8 00h 0f016h interrupt enable register 6 ie6 ? r/w 8 00h 0f017h interrupt enable register 7 ie7 ? r/w 8 00h 0f018h interrupt request register 0 irq0 ? r/w 8 00h 0f019h interrupt request register 1 irq1 ? r/w 8 00h 0f01ah interrupt request register 2 irq2 ? r/w 8 00h 0f01bh interrupt request register 3 irq3 ? r/w 8 00h 0f01ch interrupt request register 4 irq4 ? r/w 8 00h 0f01dh interrupt request register 5 irq5 ? r/w 8 00h 0f01eh interrupt request register 6 irq6 ? r/w 8 00h 0f01fh interrupt request register 7 irq7 ? r/w 8 00h
ml610q407/ml610q408/ml610q409 user's manual chapter 5 interrupt 5-3 5.2.2 interrupt enable register 1 (ie1) address: 0f011h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 ie1 ? ? ? ep04 ep03 ep02 ep01 ep00 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 ie1 is a special function regist er (sfr) to control enable/dis able for each interrupt request. when an interrupt is accepted, the master interrupt enable flag (mie) is set to ?0?, but the corresponding flag of ie1 is not reset. [description of bits] ? ep00 (bit 0) ep00 is the enable flag for the input port p00 pin interrupt (p00int). ep00 descri p tion 0 disabled ( initial value ) 1 enabled ? ep01 (bit 1) ep01 is the enable flag for the input port p01 pin interrupt (p01int). ep01 descri p tion 0 disabled ( initial value ) 1 enabled ? ep02 (bit 2) ep02 is the enable flag for the input port p02 pin interrupt (p02int). ep02 descri p tion 0 disabled ( initial value ) 1 enabled ? ep03 (bit 3) ep03 is the enable flag for the input port p03 pin interrupt (p03int). ep03 descri p tion 0 disabled ( initial value ) 1 enabled ? ep04 (bit 4) ep04 is the enable flag for the input port p04 pin interrupt (p04int). ep04 descri p tion 0 disabled ( initial value ) 1 enabled
ml610q407/ml610q408/ml610q409 user's manual chapter 5 interrupt 5-4 5.2.3 interrupt enable register 2 (ie2) address: 0f012h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 ie2 ? ? ? ? ep5 ? esio1 esio0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 ie2 is a special function regist er (sfr) to control enable/dis able for each interrupt request. when an interrupt is accepted, the master interrupt enable flag (mie) is set to ?0?, but the corresponding flag of ie2 is not reset. [description of bits] ? esio0 (bit 0) esio0 is the enable flag for the synchronous serial port 0 interrupt (sio0int). esio0 descri p tion 0 disabled ( initial value ) 1 enabled ? esio1 (bit 1) esio1 is the enable flag for the synchronous serial port 1 interrupt (sio1int). esio1 descri p tion 0 disabled ( initial value ) 1 enabled ? ep5 (bit 3) ep5 is the enable flag for the external 8 interrupt (p5int). ep5 descri p tion 0 disabled ( initial value ) 1 enabled
ml610q407/ml610q408/ml610q409 user's manual chapter 5 interrupt 5-5 5.2.4 interrupt enable register 3 (ie3) address: 0f013h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 ie3 ? ? ? ? ? ? etm1 etm0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 ie3 is a special function regist er (sfr) to control enable/dis able for each interrupt request. when an interrupt is accepted, the master interrupt enable flag (mie) is set to ?0?, but the corresponding flag of ie3 is not reset. [description of bits] ? etm0 (bit 0) etm0 is the enable flag for the timer 0 interrupt (tm0int). etm0 descri p tion 0 disabled ( initial value ) 1 enabled ? etm1 (bit 1) etm1 is the enable flag for the timer 1 interrupt (tm1int). etm1 descri p tion 0 disabled ( initial value ) 1 enabled
ml610q407/ml610q408/ml610q409 user's manual chapter 5 interrupt 5-6 5.2.5 interrupt enable register 4 (ie4) address: 0f014h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 ie4 ? ? erad ? ? emd0 ? eua0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 ie4 is a special function regist er (sfr) to control enable/dis able for each interrupt request. when an interrupt is accepted, the master interrupt enable flag (mie) is set to ?0?, but the corresponding flag of ie4 is not reset. [description of bits] ? eua0 (bit 0) eua0 is the enable flag for the uart0 interrupt (ua0int). eua0 descri p tion 0 disabled ( initial value ) 1 enabled ? emd0 (bit 2) emd0 is the enable flag for the melody 0 interrupt (md0int). emd0 descri p tion 0 disabled ( initial value ) 1 enabled ? erad (bit 5) erad is the enable flag for the rc oscillati on type a/d converter interrupt (radint). era0 descri p tion 0 disabled ( initial value ) 1 enabled
ml610q407/ml610q408/ml610q409 user's manual chapter 5 interrupt 5-7 5.2.6 interrupt enable register 5 (ie5) address: 0f015h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 ie5 ? ? etm3 etm2 ? ? ? ? r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 ie5 is a special function regist er (sfr) to control enable/dis able for each interrupt request. when an interrupt is accepted, the master interrupt enable flag (mie) is set to ?0?, but the corresponding flag of ie5 is not reset. [description of bits] ? etm2 (bit 4) etm2 is the enable flag for the timer 2 interrupt (tm2int). etm2 descri p tion 0 disabled ( initial value ) 1 enabled ? etm3 (bit 5) etm3 is the enable flag for the timer 3 interrupt (tm3int). etm3 descri p tion 0 disabled ( initial value ) 1 enabled
ml610q407/ml610q408/ml610q409 user's manual chapter 5 interrupt 5-8 5.2.7 interrupt enable register 6 (ie6) address: 0f016h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 ie6 e32h ? e128h ? ? ? ? epw0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 ie6 is a special function regist er (sfr) to control enable/dis able for each interrupt request. when an interrupt is accepted, the master interrupt enable flag (mie) is set to ?0?, but the corresponding flag of ie6 is not reset. [description of bits] ? epw0 (bit 0) epw0 is the enable flag for the pwm0 interrupt (pw0int). epw0 descri p tion 0 disabled ( initial value ) 1 enabled ? e128h (bit 5) e128h is the enable flag for the time base counter 128 hz interrupt (t128hint). e128h descri p tion 0 disabled ( initial value ) 1 enabled ? e32h (bit 7) e32h is the enable flag for the time base counter 32 hz interrupt (t32hint). e32h descri p tion 0 disabled ( initial value ) 1 enabled
ml610q407/ml610q408/ml610q409 user's manual chapter 5 interrupt 5-9 5.2.8 interrupt enable register 7 (ie7) address: 0f017h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 ie7 ? ? ? ? e2h ? ? e16h r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 ie7 is a special function regist er (sfr) to control enable/dis able for each interrupt request. when an interrupt is accepted, the master interrupt enable flag (mie) is set to ?0?, but the corresponding flag of ie7 is not reset. [description of bits] ? e16h (bit 0) e16h is the enable flag for the time base counter 16 hz interrupt (t16hint). e16h descri p tion 0 disabled ( initial value ) 1 enabled ? e2h (bit 3) e2h is the enable flag for the time base counter 2 hz interrupt (t2hint). e2h descri p tion 0 disabled ( initial value ) 1 enabled
ml610q407/ml610q408/ml610q409 user's manual chapter 5 interrupt 5-10 5.2.9 interrupt request register 0 (irq0) address: 0f018h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 irq0 ? ? ? ? ? ? ? qwdt r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 irq0 is a special function regi ster (sfr) to request an inte rrupt for each interrupt source. the watchdog timer interrupt (wdtint) is a non-maskable interrupt that do not depend on mie. in this case, an interrupt is requested to the cpu regardless of the value of the mask interrupt enable flag (mie). each irq0 request flag is set to ?1? regardless of the mie value when an interrupt is generated. by setting the irq0 request flag to ?1? by software, an interrupt can be generated. the corresponding flag of irq0 is set to ?0? by hardware when the interr upt request is accepted by the cpu. [description of bits] ? qwdt (bit 0) qwdt is the request flag for the watchdog timer interrupt (wdtint). qwdt descri p tion 0 no re q uest ( initial value ) 1 re q uest note: when an interrupt is generated by the write instruction to the interrupt request register (irq0), the interrupt shift cycle starts after the next 1 instruction is executed.
ml610q407/ml610q408/ml610q409 user's manual chapter 5 interrupt 5-11 5.2.10 interrupt request register 1 (irq1) address: 0f019h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 irq1 ? ? ? qp04 qp03 qp02 qp01 qp00 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 irq1 is a special function regi ster (sfr) to request an inte rrupt for each interrupt source. each irq1 request flag is set to ?1? rega rdless of the ie1 and mie values when an interrupt is generated. in this case, an interrupt is requested to the cpu when the related flag of the interrupt enable register (ie1) is set to ?1? and the master interrupt enable flag (mie) is set to ?1?. by setting the irq1 request flag to ?1? by software, an interrupt can be generated. the corresponding flag of irq1 is set to ?0? by hardware when the interr upt request is accepted by the cpu. [description of bits] ? qp00 (bit 0) qp00 is the request flag for the input port p00 pin interrupt (p00int). qp00 descri p tion 0 no re q uest ( initial value ) 1 re q uest ? qp01 (bit 1) qp01 is the request flag for the input port p01 pin interrupt (p01int). qp01 descri p tion 0 no re q uest ( initial value ) 1 re q uest ? qp02 (bit 2) qp02 is the request flag for the input port p02 pin interrupt (p02int). qp02 descri p tion 0 no re q uest ( initial value ) 1 re q uest ? qp03 (bit 3) qp03 is the request flag for the input port p03 pin interrupt (p03int). qp03 descri p tion 0 no re q uest ( initial value ) 1 re q uest ? qp04 (bit 4) qp04 is the request flag for the input port p04 pin interrupt (p04int). qp04 descri p tion 0 no re q uest ( initial value ) 1 re q uest
ml610q407/ml610q408/ml610q409 user's manual chapter 5 interrupt 5-12 note: when an interrupt is generated by the write instruction to the interrupt request register (irq1) or to the interrupt enable register (ie1), the interr upt shift cycle starts after the next 1 instruction is executed.
ml610q407/ml610q408/ml610q409 user's manual chapter 5 interrupt 5-13 5.2.11 interrupt request register 2 (irq2) address: 0f01ah access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 irq2 ? ? ? ? qp5 ? qsio1 qsio0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 irq2 is a special function regi ster (sfr) to request an inte rrupt for each interrupt source. each irq2 request flag is set to ?1? rega rdless of the ie2 and mie values when an interrupt is generated. in this case, an interrupt is requested to the cpu when the related flag of the interrupt enable register (ie2) is set to ?1? and the master interrupt enable flag (mie) is set to ?1?. by setting the irq2 request flag to ?1? by software, an interrupt can be generated. the corresponding flag of irq2 is set to ?0? by hardware when the interr upt request is accepted by the cpu. [description of bits] ? qsio0 (bit 0) qsio0 is the request flag for the synchronous serial port 0 interrupt (sio0int). qsio0 descri p tion 0 no re q uest ( initial value ) 1 re q uest ? qsio1 (bit 1) qsio1 is the request flag for the synchronous serial port 1 interrupt (sio1int). qsio0 descri p tion 0 no re q uest ( initial value ) 1 re q uest ? qp5 (bit 3) qp5 is the request flag for the external 8 interrupt (p5int). qp5 descri p tion 0 no re q uest ( initial value ) 1 re q uest note: when an interrupt is generated by the write instruction to the interrupt request register (irq2) or to the interrupt enable register (ie2), the interr upt shift cycle starts after the next 1 instruction is executed.
ml610q407/ml610q408/ml610q409 user's manual chapter 5 interrupt 5-14 5.2.12 interrupt request register 3 (irq3) address: 0f01bh access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 irq3 ? ? ? ? ? ? qtm1 qtm0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 irq3 is a special function regi ster (sfr) to request an inte rrupt for each interrupt source. each irq3 request flag is set to ?1? rega rdless of the ie3 and mie values when an interrupt is generated. in this case, an interrupt is requested to the cpu when the related flag of the interrupt enable register (ie3) is set to ?1? and the master interrupt enable flag (mie) is set to ?1?. by setting the irq3 request flag to ?1? by software, an interrupt can be generated. the corresponding flag of irq3 is set to ?0? by hardware when the interr upt request is accepted by the cpu. [description of bits] ? qtm0 (bit 0) qtm0 is the request flag for the timer 0 interrupt (tm0int). qtm0 descri p tion 0 no re q uest ( initial value ) 1 re q uest ? qtm1 (bit 1) qtm1 is the request flag for the timer 1 interrupt (tm1int). qtm1 descri p tion 0 no re q uest ( initial value ) 1 re q uest note: when an interrupt is generated by the write instruction to the interrupt request register (irq3) or to the interrupt enable register (ie3), the interr upt shift cycle starts after the next 1 instruction is executed.
ml610q407/ml610q408/ml610q409 user's manual chapter 5 interrupt 5-15 5.2.13 interrupt request register 4 (irq4) address: 0f01ch access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 irq4 ? ? qrad ? ? qmd0 ? qua0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 irq4 is a special function regi ster (sfr) to request an inte rrupt for each interrupt source. each irq4 request flag is set to ?1? rega rdless of the ie4 and mie values when an interrupt is generated. in this case, an interrupt is requested to the cpu when the related flag of the interrupt enable register (ie4) is set to ?1? and the master interrupt enable flag (mie) is set to ?1?. by setting the irq4 request flag to ?1? by software, an interrupt can be generated. the corresponding flag of irq4 is set to ?0? by hardware when the interr upt request is accepted by the cpu. [description of bits] ? qua0 (bit 0) qua0 is the request flag for the uart0 interrupt (ua0int). qu a 0 descri p tion 0 no re q uest ( initial value ) 1 re q uest ? qmd0 (bit 2) qmd0 is the request flag for th e melody 0 interrupt (md0int). qmd0 descri p tion 0 no re q uest ( initial value ) 1 re q uest ? qra0 (bit 5) qmd0 is the request flag for the rc oscilla tion type a/d converter interrupt (radint). qr a 0 descri p tion 0 no re q uest ( initial value ) 1 re q uest note: when an interrupt is generated by the write instruction to the interrupt request register (irq4) or to the interrupt enable register (ie4), the interr upt shift cycle starts after the next 1 instruction is executed.
ml610q407/ml610q408/ml610q409 user's manual chapter 5 interrupt 5-16 5.2.14 interrupt request register 5 (irq5) address: 0f01dh access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 irq3 ? ? qtm3 qtm2 ? ? ? ? r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 irq5 is a special function regi ster (sfr) to request an inte rrupt for each interrupt source. each irq5 request flag is set to ?1? rega rdless of the ie3 and mie values when an interrupt is generated. in this case, an interrupt is requested to the cpu when the related flag of the interrupt enable register (ie5) is set to ?1? and the master interrupt enable flag (mie) is set to ?1?. by setting the irq5 request flag to ?1? by software, an interrupt can be generated. the corresponding flag of irq5 is set to ?0? by hardware when the interr upt request is accepted by the cpu. [description of bits] ? qtm2 (bit 4) qtm2 is the request flag for the timer 2 interrupt (tm2int). qtm2 descri p tion 0 no re q uest ( initial value ) 1 re q uest ? qtm3 (bit 5) qtm3 is the request flag for the timer 3 interrupt (tm3int). qtm3 descri p tion 0 no re q uest ( initial value ) 1 re q uest note: when an interrupt is generated by the write instruction to the interrupt request register (irq5) or to the interrupt enable register (ie5), the interr upt shift cycle starts after the next 1 instruction is executed.
ml610q407/ml610q408/ml610q409 user's manual chapter 5 interrupt 5-17 5.2.15 interrupt request register 6 (irq6) address: 0f01eh access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 irq6 q32h ? q128h ? ? ? ? qpw0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 irq6 is a special function regi ster (sfr) to request an inte rrupt for each interrupt source. each irq6 request flag is set to ?1? rega rdless of the ie6 and mie values when an interrupt is generated. in this case, an interrupt is requested to the cpu when the related flag of the interrupt enable register (ie6) is set to ?1? and the master interrupt enable flag (mie) is set to ?1?. by setting the irq6 request flag to ?1? by software, an interrupt can be generated. the corresponding flag of irq6 is set to ?0? by hardware when the interr upt request is accepted by the cpu. [description of bits] ? qpw0 (bit 0) qpw0 is the request flag for the pwm0 interrupt (pw0int). qpw0 descri p tion 0 no re q uest ( initial value ) 1 re q uest ? q128h (bit 5) q128h is the request flag for the time base counter 128 hz interrupt (t128hint). q128h descri p tion 0 no re q uest ( initial value ) 1 re q uest ? q32h (bit 7) q32h is the request flag for the time base counter 32 hz interrupt (t32hint). q32h descri p tion 0 no re q uest ( initial value ) 1 re q uest note: when an interrupt is generated by the write instruction to the interrupt request register (irq6) or to the interrupt enable register (ie6), the interr upt shift cycle starts after the next 1 instruction is executed.
ml610q407/ml610q408/ml610q409 user's manual chapter 5 interrupt 5-18 5.2.16 interrupt request register 7 (irq7) address: 0f01fh access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 irq7 ? ? ? ? q2h ? ? q16h r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 irq7 is a special function regi ster (sfr) to request an inte rrupt for each interrupt source. each irq7 request flag is set to ?1? rega rdless of the ie7 and mie values when an interrupt is generated. in this case, an interrupt is requested to the cpu when the related flag of the interrupt enable register (ie7) is set to ?1? and the master interrupt enable flag (mie) is set to ?1?. by setting the irq7 request flag to ?1? by software, an interrupt can be generated. the corresponding flag of irq7 is set to ?0? by hardware when the interr upt request is accepted by the cpu. [description of bits] ? q16h (bit 0) q16h is the request flag for the time base counter 8 hz interrupt (t8hint). q16h descri p tion 0 no re q uest ( initial value ) 1 re q uest ? q2h (bit 3) q2h is the request flag for the time base counter 2 hz interrupt (t2hint). q2h descri p tion 0 no re q uest ( initial value ) 1 re q uest note: when an interrupt is generated by the write instruction to the interrupt request register (irq7) or to the interrupt enable register (ie7), the interr upt shift cycle starts after the next 1 instruction is executed.
ml610q407/ml610q408/ml610q409 user's manual chapter 5 interrupt 5-19 5.3 description of operation with the exception of the watchdog timer interrupt (wdtint), interrupt enable/disable for 20 sources is controlled by the master interrupt enable flag (mie) and the individual interrupt enable registers (ie1 to 7). wdtint is a non-maskable interrupt. when the interrupt conditions are satisfied, the cpu calls a branching destination address from the vector table determined for each interrupt source and th e interrupt shift cycle star ts to branch to the inte rrupt processing routine. table 5-1 lists the interrupt sources. table 5-1 interrupt sources priority interrupt source symbol vector table address 1 watchdog timer interrupt wdtint 0008h 2 p00 interrupt p00int 0010h 3 p01 interrupt p01int 0012h 4 p02 interrupt p02int 0014h 5 p03 interrupt p03int 0016h 6 p04 interrupt p04int 0018h 7 synchronous serial port 0 interrupt sio0int 0020h 8 synchronous serial port 1 interrupt sio1int 0022h 9 external 8 interrupt p5int 0026h 10 timer 0 interrupt tm0int 0030h 11 timer 1 interrupt tm1int 0032h 12 uart 0 interrupt ua0int 0040h 13 melody 0 interrupt md0int 0044h 14 rc oscillation type a/d converter interrupt radint 004ah 15 timer 2 interrupt tm2int 0058h 16 timer 3 interrupt tm3int 005ah 17 pwm0 interrupt pw0int 0060h 18 tbc128hz interrupt t128hint 006ah 19 tbc32hz interrupt t32hint 006eh 20 tbc16hz interrupt t16hint 0070h 21 tbc2hz interrupt t2hint 0076h note: - when multiple interrupts are generated concurrently, the interrupts are serviced accord ing to this priority and processing of low-priority interrupts is pending. - please define vector tables for all unused interrupts for fail safe.
ml610q407/ml610q408/ml610q409 user's manual chapter 5 interrupt 5-20 5.3.1 maskable interrupt processing when an interrupt is generated with the mie flag set to ?1?, the following processing is executed by hardware and the processing of program shifts to the interrupt destination. (1) transfer the program counter (pc) to elr1 (2) transfer csr to ecsr1 (3) transfer psw to epsw1 (4) set the mie flag to ?0? (5) set the elevel field to?1? (6) load the interrupt start address into pc 5.3.2 non-maskable interrupt processing when an interrupt is generated regardless of the state of mie flag, the following processing is performed by hardware and the processing of program shifts to the interrupt destination. (1) transfer pc to elr2 (2) transfer csr to ecsr2 (3) transfer psw to epsw2 (4) set the elevel field to ?2? (5) load the interrupt start address into pc 5.3.3 software interrupt processing a software interrupt is generated as required within an application program. when the swi instruction is performed within the program, a software interrupt is generated, the following processing is performed by hardware, and the processing program shifts to the interrupt destination. the vector table is specified by the swi instruction. (1) transfer pc to elr1 (2) transfer csr to ecsr1 (3) transfer psw to epsw1 (4) set the mie flag to ?0? (5) set the elevel field to?1? (6) load the interrupt start address into pc reference: for the mie flag, program counter (pc), csr, psw, and elevel, see ?nx-u8/100 co re instruction manual?.
ml610q407/ml610q408/ml610q409 user's manual chapter 5 interrupt 5-21 5.3.4 notes on interrupt routine notes are different in programming depending on whether a subroutine is called or not by the program in executing an interrupt routine, whether multiple interrupts are enabled or disabled, and whether such interrupts are maskable or non-maskable. status a: maskable interrupt is being processed a-1: when a subroutine is not called by the program in executing an interrupt routine a-1-1: when multiple interrupts are disabled ?processing immediately after the st art of interrupt routine execution no specific notes. ?processing at the end of interrupt routine execution specify the rti instruction to return the contents of the elr register to the pc and those of the epsw register to psw. a-1-2: when multiple interrupts are enabled ?processing immediately after the st art of interrupt routine execution specify "push elr, epsw" to save the interrupt return address and the psw status in the stack. ?processing at the end of interrupt routine execution specify ?pop pc, psw? instead of the rti instructi on to return the contents of the stack to pc and psw. example of description: status a-1-1 example of description: status a-1-2 intrpt_a-1-1; ; a-1-1 state intrpt_a-1-2; ; start di ; disable interrupt push elr,epsw ; save elr and epsw at the beginning : : ei ; enable interrupt : : rti ; return pc from elr : ; return psw form epsw : ; end : : pop pc,psw ; return pc from the stack ; return psw from the stack ; end
ml610q407/ml610q408/ml610q409 user's manual chapter 5 interrupt 5-22 a-2: when a subroutine is called by the program in executing an interrupt routine a-2-1: when multiple interrupts are disabled ?processing immediately after the st art of interrupt routine execution specify the ?push lr? instruction to save the subroutine return address in the stack. ?processing at the end of interrupt routine execution specify ?pop lr? immediately before the rti instruction to return from the interrupt processing after returning the subroutine return address to lr. a-2-2: when multiple interrupts are enabled ?processing immediately after the st art of interrupt routine execution specify "push lr, elr, epsw" to save the interrupt return address, the subroutine return address, and the epsw status in the stack. ?processing at the end of interrupt routine execution specify ?pop pc, psw, lr? instead of the rti instruction to return the saved data of the interrupt return address to pc, the saved data of epsw to psw, and the saved data of lr to lr. example of description: status a-2-2 intrpt_a-2-2; ; start push elr,epsw,lr ; save elr, epsw, and lr at the beginning ei ; enable interrupt : sub_1; ; : di ; disable interrupt : : : bl sub_1 ; call subroutine sub_1 : : rt ; return pc from lr pop pc,psw,lr ; return pc from the stack ; end of subroutine ; return psw from the stack ; return lr from the stack ; end
ml610q407/ml610q408/ml610q409 user's manual chapter 5 interrupt 5-23 status b: non-maskable interrupt is being processed b-1: when a subroutine is not called in an interrupt routine ?processing immediately after the start of interrupt routine execution specify "push elr, epsw" to save the interrupt return address and the psw status in the stack. ?interrupt routine execution end processing specify "pop psw, pc" to return the c ontents of the stack to pc and psw. example of description: status b-1 intrpt_c-1: ; start the interrupt routine push elr,epsw ; save elr and epsw at the beginning : : pop psw,pc ; return pc from the stack ; return psw from the stack ; return lr from the stack ; end the interrupt routine b-2: when a subroutine is called in an interrupt routine ?iprocessing immediately after th e start of interrupt routine specify "push elr, lr, epsw" to save the interrupt return address, the subroutine return address, and the epsw status in the stack. ?interrupt routine end processing specify "pop psw, pc, lr" to return the saved data of the interrupt return address to pc, the saved data of epsw to psw, and the saved data of lr to lr. example of description: status b-2 intrpt_c-2: ; start push elr,epsw,lr ; save elr, epsw, and lr at the beginning : sub_1: ; : : bl sub_1 ; call subroutine sub_1 : : rt ; return pc from lr pop psw,pc,lr ; return pc from the stack ; end of subroutine ; return psw from the stack ; return lr from the stack ; end
ml610q407/ml610q408/ml610q409 user's manual chapter 5 interrupt 5-24 5.3.5 interrupt disable state even if the interrupt conditions are sa tisfied, an interrupt may not be accepted depending on the operati ng state. this is called an interrupt disabled state. see below for the interrupt disabled state and the handling of interrupts in this state. interrupt disabled state 1:between the interrupt shift cycle and the instruction at the beginning of the interrupt routine when the interrupt conditions are satisfied in this section, an interrupt is generated immediately following the execution of the instruction at the beginning of the interrupt routine corresponding to the interrupt that has already been enabled. interrupt disabled state 2:between the dsr pr efix instruction and the next instruction when the interrupt conditions are satisfied in this section, an interrupt is generated immediately after execution of the instruction following the dsr prefix instruction. for the dsr prefix instruction, see ?nx-u8/100 core instruction manual?.
chapter 6 clock generation circuit
ml610q407/ml610q408/ml610q409 user's manual chapter 6 clock generation circuit 6-1 6. clock generation circuit 6.1 overview the clock generation circuit generates and provides a low- speed clock (lsclk), the low-speed double clock (lsclk x 2), a high-speed clock (hsclk), a system clock (sysclk), and a high-speed output clock (outclk). lsclk, lsclk x 2, and hsclk are time base clocks for the periphe ral circuits, sysclk is a basic operation clock of cpu, and outclk is a clock that is output from a port. for the outclk output port, see chapter 15, ?port 2?. for the stop mode described in this chapter, see chapter 4, "mcu control function." 6.1.1 features ? low-speed clock generation circ uit: 32.768khz crystal oscillation mode - capable of using the 32.768khz double clock lsclk x 2 (64khz) for some peripherals ? high-speed clock generation circuit - 500khz/2mhz rc oscillation mode 500khz or 2mhz rc oscillation 6.1.2 configuration figure 6-1 shows the configuration of the clock generation circuit. fcon0 : frequency control register 0 fcon1 : frequency control register 1 figure 6-1 configuration of clock generation circuit note: this lsi starts operation with the low-speed clock after power- on or a system reset. at initialization by software, set the fcon0 or fcon1 register to switch the clock to a requi red one. operation of this lsi is not guaranteed under a condition where a low-speed clock is not supplied. xt0 xt1 high-speed clock generation circuit low-speed clock (lsclk) high-speed clock (hsclk) system clock (sysclk) mpx fcon0,fcon1 data bus dividing selection 1/1,1/2,1/4,1/8 dividing selection 1/1,1/2,1/4,1/8 high-speed output clock (outclk) osc lk low-speed clock generation circuit low-speed double clock (lsclk x 2)
ml610q407/ml610q408/ml610q409 user's manual chapter 6 clock generation circuit 6-2 6.1.3 list of pins pin name input/o utput function xt0 i pin for connecting a crystal for low-speed clock. xt1 o pin for connecting a crystal for low-speed clock. 6.2 description of registers 6.2.1 list of registers address name symbol (byte) symbol (word) r/w size initial value 0f002h frequency control register 0 fcon0 r/w 8/16 33h 0f003h frequency control register 1 fcon1 fcon r/w 8 00h
ml610q407/ml610q408/ml610q409 user's manual chapter 6 clock generation circuit 6-3 6.2.2 frequency control register 0 (fcon0) address: 0f002h access: r/w access size: 8/16 bit initial value: 33h 7 6 5 4 3 2 1 0 fcon0 ? oscm2 outc1 outc0 ? ? sysc1 sysc0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 1 1 0 0 1 1 fcon0 is a special function register (sfr) to control the high- speed clock generation circuit and to select system clock. [description of bits] ? sysc1, sysc0 (bits 1, 0) the sysc1 and sysc0 bits are used to select the freque ncy of the high-speed clock (hsclk) used for system clock and peripheral circuits (including high-speed tim e base counter). osclk, 1/2osclk, 1/4osclk, or 1/8osclk can be selected. the maximum operating freque ncy guaranteed for the system clock (sysclk) of this lsi is 500 khz or 2 mhz. at system reset, 1/ 8osclk is selected. sysc1 sysc0 description 0 0 osclk 0 1 1/2osclk 1 0 1/4osclk 1 1 1/8osclk (initial value) ? outc1, outc0 (bits 5, 4) the outc1 and outc0 bits are used to select the frequency of the high-speed output clock which is output when the secondary function of the port is used. osclk, 1/2osclk, 1/4osclk, or 1/8osclk can be selected. at system reset, 1/ 8osclk is selected. outc1 outc0 description 0 0 osclk 0 1 1/2osclk 1 0 1/4osclk 1 1 1/8osclk (initial value) ? oscm2 (bit 6) this bit sets the high-speed clock oscillation frequency. 500khz or 2mhz can be selected. this bit can be written only when the high-speed clock oscillator circuit stops oscillating (during fcon1 register's enosc bit is "0"). oscm2 description 0 500khz oscillation (initial value) 1 2mhz oscillation note: internal logic voltage (v ddl ) is changed by oscm2 bit. v ddl becomes typ.1.2v when oscm2 is set to ?0? and 500khz oscillation is selected. v ddl becomes typ.1.5v when oscm2 is set to ?1? and 2mhz oscillation is selected. . ensure to write this bit when the high-speed clock oscillator circuit stops oscillating (during fcon1 register's enosc bit is "0").
ml610q407/ml610q408/ml610q409 user's manual chapter 6 clock generation circuit 6-4 6.2.3 frequency control register 1 (fcon1) address: 0f003h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 fcon1 ? ? ? ? ? enmlt enosc sysclk r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 fcon1 is a special function register (sfr) to control the high- speed clock generation circuit and to select system clock. [description of bits] ? sysclk (bit 0) the sysclk bit is used to select system clock. it a llows selection of the low-speed clock (lsclk) or hsclk (1/nosclk: n = 1, 2, 4, 8) selected by using the high-speed clock frequency select bit (sysc1, 0) of fcon0. when the oscillation of high-speed cl ock is stopped (enosc bit = ?0?), the sy sclk bit is fixed to ?0? and the low-speed clock (lsclk) is se lected for system clock. sysclk description 0 lsclk (initial value) 1 hsclk ? enosc (bit 1) the enosc bit is used to select enable/disable of the oscillation of the high-speed clock oscillator circuit. enosc description 0 stops high-speed oscillation (initial value) 1 enables high-speed oscillation ? enmlt (bit 2) the enmlt bit is used to select enable/disable of the operation of the low-speed double clock (lsclk x 2). enmlt description 0 disables low-speed double clock operation (initial value) 1 enables low-speed double clock operation
ml610q407/ml610q408/ml610q409 user's manual chapter 6 clock generation circuit 6-5 6.3 description of operation 6.3.1 low-speed clock 6.3.1.1 low-speed clock generation circuit figure 6-2 shows the circuit configuration of the low-speed clock generation circuit. for the low-speed clock generation ci rcuit, externally provide a 32.768khz crystal oscillator and capacitors (c gl and c dl ). in the stop mode, the xt0 and xt1 pins become hiz (high-impedance). when the enmlt bit of fcon1 is set to ?1?, the low-speed double clock (lsclk x 2) starts operation. figure 6-2 circuit configuration of 32.768 khz crystal oscillation mode note: install a crystal as close to the lsi as possible and make sure that signals causing noise and power supply wiring are not near the crystal and its wiring. note that oscillation may stop due to condensation. xt0 v ss c dl c gl 32.768khz crystal oscillator xt1 v ddl stop mode low-speed clock (lsclk) r f 2 enmlt control circuit
ml610q407/ml610q408/ml610q409 user's manual chapter 6 clock generation circuit 6-6 6.3.1.2 operation of low-speed clock generation circuit the low-speed clock generation circuit is activ ated by the occurrence of power on reset. after the power-on, it waits for the low-speed oscillation start time (t xtl ) and the low-speed clock (lsclk) oscillation stabilization time (8192 counts). then, the mode moves to the program run mode, the cpu starts operation, and at the same time the low-speed clock (lsclk) is supplied to the peripheral circuits. the low-speed clock generation circuit stops oscillation when it shifts to the stop mode by software. when oscillation is resumed by releasing of the stop mode by external interrupt, lsclk is supplied to the peripheral circuits after the elapse of the low-speed oscillation start period (t xtl ) and low-speed clock (lsclk) oscillation stabilization time (8192 counts). for stop mode, see chapter 4, ?mcu control function?. figure 6-3 shows the waveforms of the low-speed clock generation circuit. for the low-speed oscillation start time (t xtl ), see appendix c, ?electrical characteristics?. figure 6-3 operation of low -speed clock generation circuit note: after the power supply is turned on, cpu starts operation with the low-speed clock. after the stop mode is released, the cpu starts operation with the low-speed clock (syscl k bit = "0") or high-speed clock (sysclk bit = "1") depending on the fcon1's sysclk bit. lsclk waveform sysclk waveform stop mode lsclk supply started and cpu started t xtl : oscillation start time t xtl : oscillation start time powe r supply v dd reset lsclk supply started and cpu started external interrupt occurred low-speed oscillation 8192 counts low-speed clock lsclk low-speed oscillation 4096 counts low-speed oscillation 4096 counts low-speed oscillation 8192 counts lsclk waveform low-speed clock oscillation waveform low-speed clock oscillation waveform system clock sysclk sysclk waveform low-speed clock oscillation waveform low-speed oscillato r circuit start signal reset_vrx
ml610q407/ml610q408/ml610q409 user's manual chapter 6 clock generation circuit 6-7 6.3.2 high-speed clock the high-speed clock is supplied from the 500khz (non-"f" vers ion) or 2mhz ("f" versi on) rc oscillator circuit. 6.3.2.1 high-speed clock circuit after the oscillation is enabled (enosc set to "1"), the hi gh-speed clock (osclk) supply st arts in 16 counts of the rc oscillation clock. figure 6-4 shows the high-speed clock circuit configuration. figure 6-4 high-speed clock circuit configuration note: ?after the system reset mode is cleared, the osclk b ecomes the oscillation stopped state because the initial enosc value is "0". in the oscillation enable d (enosc set to "1") state, the osclk supply starts in 16 counts after the stop mode is released. stop mode enosc (enable oscillation) osclk (high-speed oscillation clock) v ddl rc oscillator circuits 16 counts
ml610q407/ml610q408/ml610q409 user's manual chapter 6 clock generation circuit 6-8 6.3.2.2 operation of high-speed clock generation circuit the high-speed clock generation circuit allows the start/stop control of oscillation by using the frequency control registers 0 and 1 (fcon0 and fcon1). oscillation can be started by setting the enosc bit of fcon1 to "1" after selecting a high-speed oscillation frequency with fcon0. after the start of oscillation, hsclk starts suppl y of a clock to the peripheral circuits following the elapse of the high-speed oscillation start period (t rc ) and the oscillation stabilization time of the high-speed oscillation clock (osclk). the high-speed clock generation circuit stops oscillation when it shifts to the stop mode by software. when the stop mode is released by external interrupt, hsclk supplies cl ocks to peripheral circuits following the elapse of the high-speed oscillation start period (t rc ) and the oscillation stabilization time of the high-speed clock (osclk). the oscillation stabilization time is for 16 clocks. figure 6-5 shows the waveforms of the high-speed clock generation circuit. figure 6-5 operation of high- speed clock generation circuit high-speed oscillation 16 counts t rc : high-speed oscillation start time high-speed oscillation waveform high-speed clock hsclk high-speed clock oscillation enabled enosc high-speed oscillation 16 counts high-speed oscillation started stop mode external interrupt occurred hi g h-s p eed oscillation waveform high-speed oscillation waveform program restarted time depends on the sysclk bit hsclk waveform low-speed clock oscillation waveform t xtl : low-speed oscillation start time low-speed clock oscillation waveform hsclk waveform t rc : high-speed oscillation start time high-speed oscillation sto p low-speed clock oscillation waveform low-speed oscillation 8192 counts
ml610q407/ml610q408/ml610q409 user's manual chapter 6 clock generation circuit 6-9 6.3.3 switching of system clock the system clock can be switched between high-speed clock (hsclk) and low-speed clock (lsclk) by using the frequency control regist ers (fcon0, fcon1). figure 6-6 shows the flow chart of system clock switching processing (hsclk to lsclk) and figure 6-7 shows the flow chart of system clock switching processing (lsclk to hsclk). figure 6-6 flow of system clock sw itching processing (hsclk to lsclk) note: immediately after the recovery from the stop mode, if the system clock is switched from hsclk to lsclk, the cpu becomes inactive until lsclk starts clock supply to the peripheral circuits . therefore, it is recommended to switch to lsclk after confirming that the lsclk is osc illating by checking that the time base counter interrupt request bit (q128h) is ?1?. figure 6-7 flow of system clock sw itching processing (lsclk to hsclk) note: if the system clock is switched from a low-speed clock to a high-speed clock before the high-speed clock (hsclk) starts oscillation, the cpu become s inactive until hsclk starts clock supply to the peripheral circuits. system clock switching enosc ?1? wait the oscillation stabilization time (t wait ) sysclk ?1? high-speed operation mode t wait =500 s high-speed oscillation start switches the system clock (low-speed clock to high-speed clock) yes no is high-speed clock used? continue to use the low-speed clock (lsclk). system clock switching sysclk ?0? low-speed operation mode switches the system clock (high-speed clock to low-speed clock) enosc ?0? stops high-speed oscillation (* not needed to stop in the case when the high-speed clock is used by something other than the cpu)
ml610q407/ml610q408/ml610q409 user's manual chapter 6 clock generation circuit 6-10 6.4 specifying port registers to enable the clock output function, each related port register bit needs to be set. see chapter 15, "port 2" for detail about the port registers. 6.4.1 functioning p21 (outclk) as the high-speed clock output set p21md bit (bit1 of p2mod register) to ?1? for specifyi ng the high-speed clock output as the secondary function of p21. register name p2mod register (address: 0f214h) bit 7 6 5 4 3 2 1 0 bit name - - - - - p22md p21md p20md setting value - - - - - * 1 * set the p21c1 bit (p2con1 register's bit 1) to "1" and the p21c0 bit (p2con0 register's bit 1) to "1" for specifying the state mode of the p21 pin to cmos output. register name p2con1 register (address: 0f213h) bit 7 6 5 4 3 2 1 0 bit name - - - - - p22c1 p21c1 p20c1 setting value - - - - - * 1 * register name p2con0 register (address: 0f212h) bit 7 6 5 4 3 2 1 0 bit name - - - - - p22c0 p21c0 p20c0 setting value - - - - - * 1 * the p21d bit (p2d register bit 1) data can either be "0" or "1". register name p2d register (address: 0f210h) bit 7 6 5 4 3 2 1 0 bit name - - - - - p22d p21d p20d setting value - - - - - * ** * - : bit that does not exist * : bit not related to the high-speed clock function ** : don?t care note: p21 (port 2) is an output-only port and does not have the re gister to select the data direction(input or output).
ml610q407/ml610q408/ml610q409 user's manual chapter 6 clock generation circuit 6-11 6.4.2 functioning p20 (lsclk) as the low-speed clock output set p20md bit (bit0 of p2mod register) to ?1? for specifying the low-speed clock output as the secondary function of p22. register name p2mod register (address: 0f214h) bit 7 6 5 4 3 2 1 0 bit name - - - - - p22md p21md p20md setting value - - - - - * * 1 set the p20c1 bit (p2con1 register bit 0) to "1" and the p20c0 bit (p2con0 register bit 0) to "1" for selecting the p20 pin state mode to cmos output. register name p2con1 register (address: 0f213h) bit 7 6 5 4 3 2 1 0 bit name - - - - - p22c1 p21c1 p20c1 setting value - - - - - * * 1 register name p2con0 register (address: 0f212h) bit 7 6 5 4 3 2 1 0 bit name - - - - - p22c0 p21c0 p20c0 setting value - - - - - * * 1 data of p22d bit (bit2 of p2d register) does not affect to the low speed clock output function, so don?t care the data for the function. register name p2d register (address: 0f210h) bit 7 6 5 4 3 2 1 0 bit name - - - - - p22d p21d p20d setting value - - - - - * * ** - : bit that does not exist * : bit not related to the low-speed clock function ** : don?t care note: p20 (port 2) is an output-only port and does not have the r egister to select the data direction(input or output).
chapter 7 time base counter
ml610q407/ml610q408/ml610q409 user's manual chapter 7 time base counter 7-1 7. time base counter 7.1 overview this lsi includes a low-speed time base counter (ltbc) and a high-speed time base counter (htbc) that generate base clocks for peripheral circuits. by using the time base counter, it is possible to generate events periodically. for input clocks, see chapter 6, ?clock generation circuit? . for interrupt permission, interrupt request flags, etc., described in this chapter, see chapter 5, ?interrupt?. 7.1.1 features ? ltbc generates t32khz to t1hz signals by dividing the low-speed clock (lsclk) frequency. ? ltbc allows frequency adjustment (adjustment range: approx. -488ppm to +488ppm. adjustment accuracy: approx. 0.48ppm) by using the low-speed time base c ounter frequency adjustment registers (ltbadjh and ltbadjl). ? htbc generates htb1 to htb32 signals by dividing the high-speed clock (hsclk) frequency. ? capable of generating 128hz , 32hz , 16hz , and 2hz interrupts. 7.1.2 configuration figure 7-1 and figure 7-2 show the configuration of a low- speed time base counter and a high-speed time base counter, respectively. ltbr : low-speed time base counter register ltbadjl : low-speed time base count er frequency adjustment register ltbadjh : low-speed time base count er frequency adjustment register figure 7-1 configuration of low-speed time base counter (ltbc) lsclk (32.768khz) 7bits-counter r ltbr 8bits-counter r reset (internal signal) ltbr write ltbadjl ltbdjh 8 data bus t2hz t4hz t8hz t16hz t32hz t64hz t128hz t256hz t512hz t1khz t2khz t4khz t8khz t16khz t32khz t1hz 8
.-2.-2.-2 6tfst.bovbm $ibqufs 5jnf#btf$pvoufs 7-2 htbdr : high-speed time base c ounter frequency divide register figure 7-2 configuration of high-speed time base counter note: the frequency of hsclk changes according to specified da ta in oscm2, sysc1, and sysc0 bits of frequency control register 0 (fon0). hsclk (500khz/2mhz) htbdr 1/n-counter r reset (internal signal) 8 data bus htbclk .500khz to 31khz/ 2mhz to 128khz
ml610q407/ml610q408/ml610q409 user's manual chapter 7 time base counter 7-3 7.2 description of registers 7.2.1 list of registers address name symbol (byte) symbol (word) r/w size initial value 0f00ah low-speed time base counter register ltbr r/w 8 00h 0f00bh high-speed time base counter frequency divide register htbdr r/w 8 00h 0f00ch low-speed time base counter frequency adjustment register l ltbadjl r/w 8/16 00h 0f00dh low-speed time base counter frequency adjustment register h ltbadjh ltbadj r/w 8 00h
.-2.-2.-2 6tfst.bovbm $ibqufs 5jnf#btf$pvoufs 7-4 7.2.2 low-speed time base counter register (ltbr) address: 0f00ah access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 ltbr t1hz t2hz t4hz t8hz t16hz t32hz t64hz t128hz r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 ltbr is a special function register (sfr) to read the t128hz to t1hz outputs of the low-speed time base counter. the t128hz-t1hz outputs are set to ?0? when write operation is performed for ltbr. write data is invalid. note: a tbc interrupt (128hz interrupt, 32hz interrupt, 16hz interrupt, or 2hz interrupt) may occur depending on the ltbr write timing. take this into consideration when programmi ng your software by referring to "figure 7-4 interrupt timing and reset timing by writing to ltbr."
ml610q407/ml610q408/ml610q409 user's manual chapter 7 time base counter 7-5 7.2.3 high-speed time base counter divide register (htbdr) address: 0f00bh access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 htbdr htd3 htd2 htd1 htd0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 htbdr is a special function register (sfr) to set the dividing ratio of the 4-bit, 1/n counter. [description of bits] ? htd3-htd0 (bits 3-0) the htd3-htd0 bits are used to set the dividing ratio of the 4-bit, 1/n counter. the frequency divide ratios selectable include 1/1 to 1/16. description htd3 htd2 htd1 htd0 dividing ratio frequency of htbclk (*1) 0 0 0 0 1/16 (initial value) 31khz 0 0 0 1 1/15 33khz 0 0 1 0 1/14 36khz 0 0 1 1 1/13 38khz 0 1 0 0 1/12 42khz 0 1 0 1 1/11 45khz 0 1 1 0 1/10 50khz 0 1 1 1 1/9 56khz 1 0 0 0 1/8 63khz 1 0 0 1 1/7 71khz 1 0 1 0 1/6 83khz 1 0 1 1 1/5 100khz 1 1 0 0 1/4 125khz 1 1 0 1 1/3 167khz 1 1 1 0 1/2 250khz 1 1 1 1 1/1 500khz *1: indicates the frequency when the high-sp eed oscillation clock, hsclk, is 500 khz.
.-2.-2.-2 6tfst.bovbm $ibqufs 5jnf#btf$pvoufs 7-6 7.2.4 low-speed time base counter frequency adjustment registers l and h (ltbadjl, ltbadjh) address: 0f00ch access: r/w access size: 8/16 bit initial value: 00h 7 6 5 4 3 2 1 0 ltbadjl ladj7 ladj6 ladj5 la dj4 ladj3 ladj2 ladj1 ladj0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 address: 0f00dh access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 ltbadjh ladjs ladj9 ladj8 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 ltbadjl and ltbadjh are special function re gisters (sfrs) to set the frequency adjustment values of the low-speed time base clock. [description of bits] ? ladjs, ladj9 to ladj8 (bits 2 to 0) ladj7-ladj0 (bits 7 to 0) the ladjs and ladj9 to ladj0 bits are used to adjust frequency. adjustment range: approximately -488ppm to +488ppm, adjustment accu racy: approximately 0.48ppm is possible. see section 7.3.3, ?low-speed time base counter frequency adjustment function? for the correspondence between the frequency adjustment va lues (ltbadjh, ltbadjl) and adjustment ratio.
ml610q407/ml610q408/ml610q409 user's manual chapter 7 time base counter 7-7 7.3 description of operation 7.3.1 low-speed time base counter the low-speed time base counter (ltbc) starts counting from 0000h on the lscl k falling edge after system reset. the t128hz, t32hz, t16hz, and t2hz outputs of ltbc are used as time base interrupts and an interrupt is requested on the falling edge of each output. each of ltbc outputs is also used as an operation clock for pe ripheral circuits. the output data of t128hz to t1hz of ltbc can be read fro m the low-speed time base counter register (ltbr). when reading the data, read ltbr twice and check that the two values coincide to prevent reading of undefined data during counting. figure 7-3 shows an example of program to read ltbr. lea offset ltbr ; ealtbr address mark: l r0, [ea] ; 1st read l r1, [ea] ; 2nd read ? cmp r0, r1 ; comparison for ltbr bne mark ; to mark when the values do not coincide ? : figure 7-3 programming example for reading ltbr ltbr is reset when write operation is performed and the t128h z to t1hz outputs are set to ?0?. write data is invalid. since an interrupt occurs if a falling edge occurs in the t128hz to t2hz out puts during writing to ltbr, take care in software programming. figure 7-4 shows interrupt generation tim ing and reset timing of the time base counter output by writing to ltbr. figure 7-4 interrupt timing and reset timing by writing to ltbr ltbr write t1hz t2hz t4hz t8hz t16hz t32hz t64hz t128hz t256hz t16hz indicates interrupt timing.
.-2.-2.-2 6tfst.bovbm $ibqufs 5jnf#btf$pvoufs 7-8 7.3.2 high-speed time base counter the high-speed time base counter is configured as a 4-bit 1/n counter (n = 1 to 16). in the 4-bit 1/n counter, the divided clock (1/16 x hsclk to 1/1 x hsclk) selected by the high-speed time base counter divide register (htbdr) is generated as htbclk. htbclk is used as a timer and also as an operation clock of pwm. figure 7-5 shows the output waveform of htbclk. figure 7-5 output waveform of htbclk high-speed time base counter divide register high-speed hsclk 1/n counter output htbclk 1/1 1/2 1/3 0fh 0eh 0dh htbdr
ml610q407/ml610q408/ml610q409 user's manual chapter 7 time base counter 7-9 7.3.3 low-speed time base counter frequency adjustment function frequency adjustment (adjustment range: approx. -488ppm to +488ppm. adjustment accuracy: approx. 0.48ppm) is possible for outputs of t8khz to t1hz of ltbc by using th e low-speed time base counter frequency adjust registers (ltbadjh and ltbadjl). table7-1 shows correspondence between the frequency adjust ment values (ltbadjh, ltbadjl) and adjustment ratio. table 7-1 correspondence between frequency adjustment values (ltbadjh, ltbadjl) and adjustment ratio ladj10 ? 0 hexadeci mal frequency adjustment ratio (ppm) 0 1 1 1 1 1 1 1 1 1 1 3ffh +487.80 0 1 1 1 1 1 1 1 1 1 0 3feh +487.33 0 0 0 0 0 0 0 0 0 1 1 003h +1.43 0 0 0 0 0 0 0 0 0 1 0 002h +0.95 0 0 0 0 0 0 0 0 0 0 1 001h +0.48 0 0 0 0 0 0 0 0 0 0 0 000h 0 1 1 1 1 1 1 1 1 1 1 1 7ffh -0.48 1 1 1 1 1 1 1 1 1 1 0 7feh -0.95 1 0 0 0 0 0 0 0 0 0 1 401h -487.80 1 0 0 0 0 0 0 0 0 0 0 400h -488.28 the adjustment values (ladj10 to ladj0) to be se t in ltbadjh and ltbadjl can be obtained by using the following equations: adjustment value 1 frequency adjustment ratio x 2097152 (decimal) 1 frequency adjustment ratio x 200000h (hexadecimal) example 1: when adjusting +15.0ppm (when the clock loses) adjustment value 1 +15.0ppm x 2097152 (decimal) 1 +15.010 -6 2097152 1 +31.45728 (decimal) 01fh (hexadecimal) example 2: when adjusting ? 25.5ppm (when the clock gains) adjustment value 1 ? 25.5ppm x 2097152 (decimal) 1 ? 25.510-62097152 1 ? 53.477376 (decimal) 7cch (hexadecimal) note: the low-speed clock (lsclk) and the outputs of t32khz and t16khz of ltbc are not adjusted by the frequency adjust function. the frequency adjustment accuracy does not guarantee the accuracy including the frequency variation of the crystal oscillation (32.768khz) due to temperature variations.
.-2.-2.-2 6tfst.bovbm $ibqufs 5jnf#btf$pvoufs 7-10 7.3.4 a signal generation for 16-bit timer 2-3 frequency measurement mode a signal (437c) used for 16-bit timer 0-1 frequency measur ement mode is generated from the output clock of the low-speed time base counter. see chapter 9, ?timer? for more detail about the frequency measurement mode. figure 7-6 configuration of frequency measur ement mode clock (437c) generation circuit lsclk tbc 16khz 8khz 4khz 2khz 1khz 512hz 256hz 128hz 64hz decoder d q 437c (supplied to timers 2 and 3)
chapter 8 capture
ml610q407/ml610q408/ml610q409 user's manual chapter 8 capture 8-1 8. capture 8.1 overview this lsi has two channels of capture circuits that capture the t4khz to t32hz signals of the low-speed time base counter (ltbc) to the capture data register at the occurrence of p00 and p01 interrupts. the circuits capture timings at which each interrupt occurred, based on th e time from the time base counter. it can also read out the t4khz to t32hz signals of the low-speed time base counter (ltbc) at any timing. for the external interrupt (p00int, p01int) from the p00 or p01 pin, see chapter 5, "interrupt" and chapter 14, "port 0". 8.1.1 features ? time base capture x 2 channels (4096hz to 32hz) 8.1.2 configuration figure 8-1 shows the configuration of the capture circuit. capcon : capture control register capstat : capture status register capr0 : capture data register 0 capr1 : capture data register 1 captb : capture time base data register figure 8-1 configuration of capture circuit 8.1.3 list of pins pin name i/o function p00/cap0 i capture 0 input pin used as the secondary func tion of the p00 pin. p01/cap1 i capture 1 input pin used as the secondary func tion of the p01 pin. cp1f cp0f capstat capture contoroller r capr1 ltbc write capr1 8 8 data bus t32hz t64hz t128hz t256hz t512hz t1khz t4khz t2khz lsclk capr0 p01int p00int write capr0 r interrupt request signal capcon (32.768khz) 8 captb
ml610q407/ml610q408/ml610q409 user's manual chapter 8 capture 8-2 8.2 description of registers 8.2.1 list of registers address name symbol (byte) symbol (word) r/w size initial value 0f090h capture control regi ster capcon ? r/w 8 00h 0f091h capture status regi ster capstat ? r 8 00h 0f092h capture data regist er 0 capr0 ? r/w 8 00h 0f093h capture data regist er 1 capr1 ? r/w 8 00h 0f094h capture time base data r egister captb ? r 8 undefined
ml610q407/ml610q408/ml610q409 user's manual chapter 8 capture 8-3 8.2.2 capture control register (capcon) address: 0f090h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 capcon ? ? ? ? ? ? ecap1 ecap0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 capcon is a special functi on register (sfr) to control the capture circuit. [description of bits] ? ecap0 (bit 0) the ecap0 bit is used to start or stop the operation of capture 0. ecap0 description 0 stops the capture 0 operat ion. (initial value) 1 starts the capt ure 0 operation. ? ecap1 (bit 1) the ecap1 bit is used to start or stop the operation of capture 1. ecap1 description 0 stops the capture 1 operat ion. (initial value) 1 starts the capt ure 1 operation.
ml610q407/ml610q408/ml610q409 user's manual chapter 8 capture 8-4 8.2.3 capture status register (capstat) address: 0f091h access: r access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 capstat ? ? ? ? ? ? capf1 capf0 r/w r r r r r r r r initial value 0 0 0 0 0 0 0 0 capstat is a read-only, special f unction register (sfr) to indicate a state of the capture circuit. [description of bits] ? capf0 (bit 0) the capf0 bit is the flag to indicate wh ether data is captured in capture data register 0 (carp0) or not. when the capf0 bit is set to "1", it indicates that data is captured in capture data register 0 (capr0). when the capf0 bit is set to "1", the next capture opera tion is stopped. so perform the write operation to capture data register 0 (capr0) to clear the capf0 bit to "0". capf0 description 0 no capture 0 latch (initial value) 1 capture 0 latch ? capf1 (bit 1) the capf1 bit is the flag to indicate wh ether data is captured in capture data register 0 (carp1) or not. when the capf0 bit is set to "1", it indicates that data is captured in capture data register 0 (capr1). when the capf1 bit is set to "1", the next capture opera tion is stopped. so perform the write operation to capture data register 1 (capr1) to clear the capf0 bit to "0". capf1 description 0 no capture 1 latch (initial value) 1 capture 1 latch
ml610q407/ml610q408/ml610q409 user's manual chapter 8 capture 8-5 8.2.4 capture data register 0 (capr0) address: 0f092h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 capr0 cp07 cp06 cp05 cp04 cp03 cp02 cp01 cp00 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 capr0 is a register in which capture data is stored. the t4khz to t32hz signals of the low-speed time base c ounter (ltbc) are captured when the p00 interrupt request is generated with the capf0 flag (bit 0 of the capstat register) set to "0". writing to capr0 sets the capf0 flag of capstat to "0". the value of capr0 does not change even if data is written to it.
ml610q407/ml610q408/ml610q409 user's manual chapter 8 capture 8-6 8.2.5 capture data register 1 (capr1) address: 0f093h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 capr1 cp17 cp16 cp15 cp14 cp13 cp12 cp11 cp10 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 capr1 is a register in which capture data is stored. the t4khz to t32hz signals of the low-speed time base c ounter (ltbc) are captured when the p01 interrupt request is generated with the capf1 flag (bit 1 of the capstat register) set to "0". writing to capr1 sets the capf1 flag of capstat to "0". the value of capr1 does not change even if data is written to it.
ml610q407/ml610q408/ml610q409 user's manual chapter 8 capture 8-7 8.2.6 capture time base data register (captb) address: 0f094h access: r access size: 8-bit initial value: undefined 7 6 5 4 3 2 1 0 captb cptb7 cptb6 cptb5 cptb4 cptb3 cptb2 cptb1 cptb0 r r r r r r r r r initial value x x x x x x x x captb is a special function register (sfr) to read the t4khz to t32hz outputs of the low-speed time base counter (ltbc). the initial value varies depending on the state of the t4khz to t32hz outputs of the low-speed time base counter (ltbc) at the timing when this register is read. when reading the data, read this register twice and check that the two values coincide to prevent reading of undefined data during counting.
ml610q407/ml610q408/ml610q409 user's manual chapter 8 capture 8-8 8.3 description of operation the capture circuit starts the capture operation by setting the ecap0 or ecap1 bit of the capture control register (capcon). when the input trigger from the p00 or p01 pin selected by the external interrupt control register 0 or 1 (exicon0 or exicon1) is generated and the p00 or p01 interrupt request flag (qp00 or qp01) is set to ?1?, the t4khz to t32hz signals of the low-speed time base counter (ltbc) are captured in the capture data register 0 or 1 (capr0 or capr1) on the next low-speed clock (lsclk) falling edge and the at the same time, the capture fl ag (capf0 or capf1) of the capture status register (capstat) is set to ?1?. when the capture flag (capf0, capf1) is ?1?, the following capture operation stops. the value, once captured by software into the capture data register 0 or 1 (cap r0, capr1), is read to the cpu. then, in preparation for the next capture operation, the writing operati on is performed to the applicable capture data register 0 or 1 (capr0, capr1)(write data is meaningless), the capture flag (capf0, capf1) is cleared to "0", then the next p00 or p01 interrupt is waited. figure 8-2 shows the timing of the capture operation. figure 8-2 timing diagram of capture operation note: when cpu is operating on the high-speed clock (hsclk), check that the capture flag (capf0, capf1) is set to "1" after the p00 or p01 interrupt request is generated and th en read capture data register 0 or 1 (capr0, capr1). system clock sysclk capf0, capf1 qp00, qp01 interrupt request flag p00 and p01 pins ltbc (t4khz to t32hz) capr0, capr1 lsclk (32.768khz) n n+1 n+1 n+1 write capr0, 1 (writing operation) xx
chapter 9 timer
ml610q407/ml610q408/ml610q409 user's manual chapter 9 timer 9-1 9. timer 9.1 overview this lsi includes 4 channels of 8-bit timers. for input clocks, see chapter 6, ?clock generation circuit?. 9.1.1 features ? the timer interrupt (tmnint) is generated when the values of timer counter register (tmnc, n=0 to 3) and timer data register (tmnd) coincide. ? a timer configured by combining timer 0 and timer 1 or timer 2 and timer 3 can be used as a 16-bit timer. ? for the timer clock, the low-speed clock (lsclk), high-speed time base clock (htbclk), or external clock can be selected. ? a 16bit-timer 2 & 3 has clock frequency measuremen t mode, which can count htbclk and generates the timer interrupt (tm3int) when the count ends. using the count data to know the frequency by so ftware can determine more accurate baud-rate. 9.1.2 configuration figure 9-1 shows the configuration of the timers. tmncon0 : timer control register 0 tmncon1 : timer control register 1 tmmd, tmnd : timer data register tmmc, tmnc : timer counter register (a) in 8-bit timer mode (timers 0 to 3) (b) in 16-bit timer mode (timers 0 to 3) tmnc data bus tmmint lsclk tmncon0 tmncon1 r matched comparator htbclk write tmmc tnck write tmnc 8 8 8 8 tmnd tmmd tmmc r 88 16 8 8 16 external clock p04/t02p0ck p44/t02p0ck tmmc latch read tmnc { n,m} = {0,1},{2,3} tmnc 8 data bus tmnint lsclk tmncon0 tmncon1 r matched tmnd comparator 8 htbclk 8 n=0 3 write tmnc tnck 8 external clock p04/t02p0ck p44/t02p0ck p45/t13ck
ml610q407/ml610q408/ml610q409 user's manual chapter 9 timer 9-2 (c) frequency measurement mode with 16 bit timer(timer2 to 3) figure 9-1 timer configuration 9.1.3 list of pins pin name i/o function p04/t02p0ck i external clock input pin 8bit timer mode : used for timer0 or timer2 16bit timer mode : used for timer0 to timer1 or time r2 to timer3. p44/t02p0ck i external clock input pin 8bit timer mode : used for timer0 or timer2 16bit timer mode : used for timer0 to timer1 or time r2 to timer3. p45/t13ck i external clock input pin 8bit timer mode : used for timer1 or timer3 tm2c data bus tm3nt lsclk tm2con0 tm2con1 r htbclk write tm3c t2ck write tm2c 8 8 tm3c r 8 external clock p04/t02p0ck p44/t02p0ck tm3c latch read tm2c counter 16khz 8khz 4khz 2khz 1khz 512hz 256hz 128hz 64hz 436cycle at 32khz decoder 64hz d q 437c low-speed time base counter (ltbc)
ml610q407/ml610q408/ml610q409 user's manual chapter 9 timer 9-3 9.2 description of registers 9.2.1 list of registers address name symbol (byte) symbol (word) r/w size initial value 0f030h timer 0 data register tm0d r/w 8/16 0ffh 0f031h timer 0 counter register tm0c tm0dc r/w 8 00h 0f032h timer 0 control register 0 tm0con0 r/w 8/16 00h 0f033h timer 0 control register 1 tm0con1 tm0con r/w 8 00h 0f034h timer 1 data register tm1d r/w 8/16 0ffh 0f035h timer 1 counter register tm1c tm1dc r/w 8 00h 0f036h timer 1 control register 0 tm1con0 r/w 8/16 00h 0f037h timer 1 control register 1 tm1con1 tm1con r/w 8 00h 0f038h timer 2 data register tm2d r/w 8/16 0ffh 0f039h timer 2 counter register tm2c tm2dc r/w 8 00h 0f03ah timer 2 control regist er 0 tm2con0 r/w 8/16 0a0h 0f03bh timer 2 control register 1 tm2con1 tm2con r/w 8 00h 0f03ch timer 3 data register tm3d r/w 8/16 0ffh 0f03dh timer 3 counter register tm3c tm3dc r/w 8 00h 0f03eh timer 3 control regist er 0 tm3con0 r/w 8/16 00h 0f03fh timer 3 control register 1 tm3con1 tm3con r/w 8 00h
ml610q407/ml610q408/ml610q409 user's manual chapter 9 timer 9-4 9.2.2 timer 0 data register (tm0d) address: 0f030h access: r/w access size: 8-bit initial value: 0ffh 7 6 5 4 3 2 1 0 tm0d t0d7 t0d6 t0d5 t0d4 t0d3 t0d2 t0d1 t0d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 1 1 1 1 1 1 1 1 tm0d is a special function register (sfr) to set the value to be compared with the timer 0 counter register (tm0c) value. note: set tm0d when the timer stops(when t0stat bit of tm0con1 register is ?0?). when ?00h? is written in tm0d, tm0d is set to ?01h?.
ml610q407/ml610q408/ml610q409 user's manual chapter 9 timer 9-5 9.2.3 timer 1 data register (tm1d) address: 0f034h access: r/w access size: 8-bit initial value: 0ffh 7 6 5 4 3 2 1 0 tm1d t1d7 t1d6 t1d5 t1d4 t1d3 t1d2 t1d1 t1d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 1 1 1 1 1 1 1 1 tm1d is a special function register (sfr) to set the value to be compared with the value of the timer 1 counter register (tm1c). note: set tm1d when the timer stops(when t1stat bit of tm1con1 register is ?0?). when ?00h? is written in tm1d, tm1d is set to ?01h?.
ml610q407/ml610q408/ml610q409 user's manual chapter 9 timer 9-6 9.2.4 timer 2 data register (tm2d) address: 0f038h access: r/w access size: 8-bit initial value: 0ffh 7 6 5 4 3 2 1 0 tm2d t2d7 t2d6 t2d5 t2d4 t2d3 t2d2 t2d1 t2d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 1 1 1 1 1 1 1 1 tm2d is a special function register (sfr) to set the value to be compared with the value of the timer 2 counter register (tm2c). note: set tm2d when the timer stops(when t2stat bit of tm2con1 register is ?0?). when ?00h? is written in tm2d, tm2d is set to ?01h?.
ml610q407/ml610q408/ml610q409 user's manual chapter 9 timer 9-7 9.2.5 timer 3 data register (tm3d) address: 0f03ch access: r/w access size: 8-bit initial value: 0ffh 7 6 5 4 3 2 1 0 tm3d t3d7 t3d6 t3d5 t3d4 t3d3 t3d2 t3d1 t3d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 1 1 1 1 1 1 1 1 tm3d is a special function register (sfr) to set the value to be compared with the value of the timer 3 counter register (tm3c). note: set tm3d when the timer stops(when t3st at bit of tm3con1 register is ?0?). when ?00h? is written in tm3d , tm3d is set to ?01h?.
ml610q407/ml610q408/ml610q409 user's manual chapter 9 timer 9-8 9.2.6 timer 0 counter register (tm0c) address: 0f031h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 tm0c t0c7 t0c6 t0c5 t0c4 t0c3 t0c2 t0c1 t0c0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 tm0c is a special function register (sfr) that functions as an 8-bit binary counter. when write operation to tm0c is performed, tm0c is set to ?00h?. the data that is written is meaningless. in 16-bit timer mode and 16-bit timer frequency measuremen t mode, if write operation is performed to either the low-order tm0c or high-order tm1c, both the low-order and the high-order are set to ?0000h?. during timer operation, the tm0c content may not be read depending on the conditions of the timer clock and the system clock. table 9-1 shows whether a tm0c read is enabled or disabled during timer operation for each condition of the timer clock and system clock. table 9-1 tm0c read enable/disable during timer operation timer clock t0ck system clock sysclk tm0c read enable/disable lsclk lsclk read enabled. lsclk hsclk read enabled. however, to prev ent the reading of undefined data during incremental count ing, read tm0c twice and check that the results match. htbclk lsclk read disabled. htbclk hsclk read enabled. lsclk external clock hsclk read disabled.
ml610q407/ml610q408/ml610q409 user's manual chapter 9 timer 9-9 9.2.7 timer 1 counter register (tm1c) address: 0f035h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 tm1c t1c7 t1c6 t1c5 t1c4 t1c3 t1c2 t1c1 t1c0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 tm1c is a special function register (sfr) that functions as an 8-bit binary counter. when write operation to tm1c is performed, tm1c is set to ?00h?. the data that is written is meaningless. in 16-bit timer mode, if write operation is performed to either the low-order tm0c or high-order tm1c, both the low order and the high order are set to ?0000h?. when reading tm1c in 16-bit timer mode, be sure to read tm0c first since the count value of tm1c is stored in the tm1c latch when tm0c is read. during timer operation, the tm1c content may not be read depending on the conditions of the timer clock and the system clock. table 9-2 shows whether a tm1c read is enabled or disabled during timer operation for each condition of the timer clock and system clock. table 9-2 tm1c read enable/disable during timer operation timer clock t1ck system clock sysclk tm1c read enable/disable lsclk lsclk read enabled. lsclk hsclk read enabled. however, to prev ent the reading of undefined data during incremental count ing, read tm1c twice and check that the results match. htbclk lsclk read disabled. htbclk hsclk read enabled. lsclk external clock hsclk read disabled.
ml610q407/ml610q408/ml610q409 user's manual chapter 9 timer 9-10 9.2.8 timer 2 counter register (tm2c) address: 0f039h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 tm2c t2c7 t2c6 t2c5 t2c4 t2c3 t2c2 t2c1 t2c0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 tm2c is a special function register (sfr) that functions as an 8-bit binary counter. when write operation to tm2c is performed, tm2c is set to ?00h?. the data that is written is meaningless. in 16-bit timer mode and 16-bit timer frequency measuremen t mode, if write operation is performed to either the low-order tm2c or high-order tm3c, both the low order and the high order are set to ?0000h?. during timer operation, the tm2c content may not be read depending on the conditions of the timer clock and the system clock. table 9-3 shows whether a tm2c read is enabled or disabled during timer operation for each condition of the timer clock and system clock. table 9-3 tm2c read enable/disable during timer operation timer clock t2ck system clock sysclk tm2c read enable/disable lsclk lsclk read enabled. lsclk hsclk read enabled. however, to prev ent the reading of undefined data during incremental count ing, read tm2c twice and check that the results match. htbclk lsclk read disabled. htbclk hsclk read enabled. lsclk external clock hsclk read disabled.
ml610q407/ml610q408/ml610q409 user's manual chapter 9 timer 9-11 9.2.9 timer 3 counter register (tm3c) address: 0f03dh access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 tm3c t3c7 t3c6 t3c5 t3c4 t3c3 t3c2 t3c1 t3c0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 tm3c is a special function register (sfr) that functions as an 8-bit binary counter. when write operation to tm3c is performed, tm3c is set to ?00h?. the data that is written is meaningless. in 16-bit timer mode and 16-bit timer frequency measuremen t mode, if write operation is performed to either the low-order (tm2c) or high-order (tm3c), both the low order and the high order are set to ?0000h?. when reading tm3c in 16-bit timer mode, be sure to read tm2c first since the count value of tm3c is stored in the tm3c latch when tm2c is read. during timer operation, the tm3c content may not be read depending on the conditions of the timer clock and the system clock. table 9-4 shows whether a tm3c read is enabled or disabled during timer operation for each condition of the timer clock and system clock. table 9-4 tm3c read enable/disable during timer operation timer clock t3ck system clock sysclk tm3c read enable/disable lsclk lsclk read enabled. lsclk hsclk read enabled. however, to prev ent the reading of undefined data during incremental count ing, read tm3c twice and check that the results match. htbclk lsclk read disabled. htbclk hsclk read enabled. lsclk external clock hsclk read disabled.
ml610q407/ml610q408/ml610q409 user's manual chapter 9 timer 9-12 9.2.10 timer 0 control register 0 (tm0con0) address: 0f032h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 tm0con0 ? ? ? ? ? t01m16 t0cs1 t0cs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 tm0con0 is a special function register (sfr) to control the timer 0. rewrite tm0con0 while the timer 0 is stopped (t0stat of the tm0con1 register is ?0?). [description of bits] ? t0cs1, t0cs0 (bits 1, 0) the t0cs1 and t0cs0 bits are used for selecting the operation clock of timer 0. lsclk, htbclk, or the external clock (p04/t02p0ck, p44/t02p0ck) can be selected by these bits. t0cs1 t0cs0 description 0 0 lsclk (initial value) 0 1 htbclk 1 0 external clock (p04/t02p0ck) 1 1 external clock (p44/t02p0ck) ? t01m16 (bit 2) the t01m16 bit is used for selecting the operating mode of timer 0 and timer 1. in 8-bit timer mode, each of timer 0 and timer 1 operates independently as a 8-bit timer. in 16-bit timer mode, timer 0 and timer 1 are connected and they operate as a 16-bit timer. in 16-bit timer mode, timer 1 is incremented by a timer 0 overflow signal. a timer 0 interrupt (tm0int) is not generated. t01m16 descri p tion 0 8-bit timer mode ( initial value ) 1 16-bit timer mode
ml610q407/ml610q408/ml610q409 user's manual chapter 9 timer 9-13 9.2.11 timer 1 control register 0 (tm1con0) address: 0f036h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 tm1con0 ? ? ? ? ? ? t1cs1 t1cs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 tm1con0 is a special function register (sfr) to control the timer 1. rewrite tm1con0 while the timer 1 is stopped (t1stat of the tm1con1 register is ?0?). [description of bits] ? t1cs1, t1cs0 (bits 1, 0) the t1cs1 and t1cs0 bits are used for selecting the operation clock of timer 1. lsclk, htbclk, or the external clock (p45/t13ck) can be selected by these bits. in cases where the 16-bit timer mode has been selected by setting t01m16 of tm0con to ?1?, the values of t1cs1 and t1cs0 are invalid. t1cs1 t1cs0 description 0 0 lsclk (initial value) 0 1 htbclk 1 0 prohibited 1 1 external clock (p45/t13ck)
ml610q407/ml610q408/ml610q409 user's manual chapter 9 timer 9-14 9.2.12 timer 2 control register 0 (tm2con0) address: 0f03ah access: r/w access size: 8-bit initial value: a0h 7 6 5 4 3 2 1 0 tm2con0 t2fma7 t2fma6 t2fma5 t2fma4 t23mfm t23m16 t2cs1 t2cs0 r/w r r r r r/w r/w r/w r/w initial value 1 0 1 0 0 0 0 0 tm2con0 is a special function register (sfr) to control the timer 2. rewrite tm2con0 while the timer 2 is stopped (t2stat of the tm2con1 register is ?0?). [description of bits] ? t2cs1, t2cs0 (bits 1, 0) the t2cs1 and t2cs0 bits are used for selecting the operation clock of timer 2. lsclk, htbclk, or the external clock (p04/t02p0ck, p44/t02p0ck) can be selected by these bits. t2cs1 t2cs0 description 0 0 lsclk (initial value) 0 1 htbclk 1 0 external clock (p04/t02p0ck) 1 1 external clock (p44/t02p0ck) ? t23mfm, t23m16 (bit 3, 2) the t23mfm bit and t23m16 bit is used for selec ting the operating mode of timer 2 and timer 3.. in 8-bit timer mode, each of timer 0 and timer 1 operates independently as a 8-bit timer. in 16-bit timer mode, timer 2 and timer 3 are connected and they operate as a 16-bit timer. in 16-bit timer mode, timer 3 is incremented by a timer 2 overflow signal. a timer 2 interrupt (tm2int) is not generated. in 16-bit timer frequency measurement mode, timer 2 and timer 3 are connected and they operate as a 16-bit clock counter to measure the frequency. a timer 2 interrupt (tm2int) is not generated. when this lsi does not have the frequency measuremen t function (t2fma7 to t2fma5 bit values are not "1010"), the t23mfm bit is read-only and the readout is always "0" regardless of the write access value. t23mfm t23m16 descri p tion 0 0 8-bit timer mode (initial value) 0 1 16-bit timer mode 1 0 prohibited 1 1 16-bit timer fre q uenc y measurement mode ? t2fma7 to t2fma4 (bit 7 to 4) t2fma7 to t2fma4 are read-only registers that show whether the frequency measurement function is provided. the readout is always "0a". t2fma7 t2fma6 t2fma5 t2fma4 descri p tion 1 0 1 0 the fre q uenc y measurement mode is available
ml610q407/ml610q408/ml610q409 user's manual chapter 9 timer 9-15 9.2.13 timer 3 control register 0 (tm3con0) address: 0f03eh access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 tm3con0 ? ? ? ? ? ? t3cs1 t3cs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 tm3con0 is a special function register (sfr) to control the timer 3. rewrite tm3con0 while the timer 3 is stopped (t3stat of the tm3con1 register is ?0?). [description of bits] ? t3cs1, t3cs0 (bits 1, 0) the t3cs1 and t3cs0 bits are used for selecting the operation clock of timer 3. lsclk, htbclk, or the external clock (p44/t13ck) can be selected by these bits. in cases where the 16-bit timer mode has been selected by setting t23m16 of tm2con to ?1?, the values of t3cs1 and t3cs0 are invalid. t3cs1 t3cs0 description 0 0 lsclk (initial value) 0 1 htbclk 1 0 prohibited 1 1 external clock (p45/t13ck)
ml610q407/ml610q408/ml610q409 user's manual chapter 9 timer 9-16 9.2.14 timer 0 control register 1 (tm0con1) address: 0f033 access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 tm0con1 t0stat ? ? ? ? ? ? t0run r/w r r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 tm0con1 is a special function register (sfr) to control the timer 0. [description of bits] ? t0run (bit 0) the t0run bit is used for controlling stop/start of timer 0. t0run description 0 stops counting. 1 starts counting. ? t0stat (bit 7) the t0stat bit is used for indicating ?counti ng stopped?/?counting in progress? of timer 0. t0stat description 0 counting stopped. 1 counting in progress.
ml610q407/ml610q408/ml610q409 user's manual chapter 9 timer 9-17 9.2.15 timer 1 control register 1 (tm1con1) address: 0f037h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 tm1con1 t1stat ? ? ? ? ? ? t1run r/w r r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 tm1con1 is a special function register (sfr) to control the timer 1. [description of bits] ? t1run (bit 0) the t1run bit is used for controlling count stop/start of timer 1. in 16-bit timer mode, be sure to set this bit to ?0?. regardless of the t1run value, the timer 1 counts up by the timer 0 overflow signal. t1run description 0 stops counting. 1 starts counting. ? t1stat (bit 7) the t1stat bit is used for indicating ?counti ng stopped?/?counting in progress? of timer 1. in 16-bit timer mode, this bit will read ?0?. t1stat description 0 counting stopped. 1 counting in progress.
ml610q407/ml610q408/ml610q409 user's manual chapter 9 timer 9-18 9.2.16 timer 2 control register 1 (tm2con1) address: 0f03bh access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 tm2con1 t2stat ? ? ? ? ? ? t2run r/w r r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 tm2con1 is a special function register (sfr) to control the timer 2. [description of bits] ? t2run (bit 0) the t2run bit is used for controlling stop/start of timer 2. setting the t2run bit can force can cel the counting in the 16-bit timer frequency measurement mode. in that case, tm3int does not occur. t2run description 0 in timer mode: stops counting. in frequency measurement mode: stops measurement 1 in timer mode: starts counting. in frequency measurement mode: starts measurement ? t2stat (bit 7) the t2stat bit is used for indicating ?counti ng stopped?/?counting in progress? of timer 2. t2stat description 0 in timer mode: count halted. in fr equency measurement mode: measurement halted 1 in timer mode: counting in progress. in frequency measurement mode: measuring
ml610q407/ml610q408/ml610q409 user's manual chapter 9 timer 9-19 9.2.17 timer 3 control register 1 (tm3con1) address: 0f03fh access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 tm3con1 t3stat ? ? ? ? ? ? t3run r/w r r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 tm3con1 is a special function register (sfr) to control the timer 3. [description of bits] ? t3run (bit 0) the t3run bit is used for controlling stop/start of timer 3. in 16-bit timer mode and 16-bit timer frequency measurement mode, be sure to set this bit to ?0?. regardless of the t3run value, the timer 3 counts up by the timer 2 overflow signal. in 16-bit timer frequency measurement mode, be sure to set this bit to ?0? also. t3run description 0 stops counting. 1 starts counting. ? t3stat (bit 7) the t3stat bit is used for indicating ?counti ng stopped?/?counting in progress? of timer 3. in 16-bit timer mode and 16-bit timer frequency measurement mode, this bit will return ?0?. t3stat description 0 counting stopped. 1 counting in progress.
ml610q407/ml610q408/ml610q409 user's manual chapter 9 timer 9-20 9.3 description of operation 9.3.1 timer mode operation the timer counters (tmnc) are set to an operating state (tns tat are set to ?1?) on the fi rst falling edge of the timer clocks (tnck) that are selected by the timer 0 to 3 control register 0 (tmncon0) when the tnrun bits of timer 0 to 3 control register 1 (tmncon1) are set to ?1? and increment the count value on the 2nd falling. when the count value of tm0 to tm3c and the timer 0 to 3 data register (tmnd) coincide, timer 0 to 3 interrupt (tmnint) occurs on the next timer clock falling edge, tmnc are reset to ?00h? and incremental counting continues. when the tnrun bits are set to ?0?, tmnc stop counting after counting once the falling of the timer clock (tnck). confirm that tmnc has been stopped by checking that the tnstat bit of the timer 0?3 control register 1 (tmncon1) is ?0?. when the tnrun bits are set to ?1 ? again, tmn restart incremental counting from the previous values. to initialize tmnc to ?00h?, perform write operation in tmnc. the timer interrupt period (t tmi ) is expressed by the following equation. tmnd + 1 t tmi = tnck (hz) (n=03) tmnd: timer 0 to 3 data register (tmnd) setting value (01h to 0ffh) tnck: clock frequency selected by the timer 0 to 3 control register 0 (tmncon0) after the tnrun bits are set to ?1?, timer s are synchronized by the timer clock and counting starts so that an error of a maximum of 1 clock period occurs until the first timer inte rrupt. the timer interrupt periods from the second time are constant. figure 9-2 shows the operation timing diagram of timer 0 to 3. figure 9-2 operation timing diagram of timer 0 to 3 note: even if ?0? is written to the tnrun b its, counting operation continues up to the falling edge (the timer 0 to 3 status flag (tnsta) is in a ?1? state) of the next timer clock pulse. therefore, the timer 0 to 3 interrupt (tmnint) may occur. tmnc xx 00 88 tmnd tmnint tnstat write tmnc tnck tnrun 01 02 87 88 00 62 5f 60 61 01 88 88 (n=0 3) t tmi
ml610q407/ml610q408/ml610q409 user's manual chapter 9 timer 9-21 9.3.2 16-bit timer frequency measurement mode operation the frequency measurement mode in 16-bit timer 2&3, is used to count the frequency of 500khz rc oscillation clock which typically has temperature variation and production tolerance. using the frequency measurement mode can make better accu racy for uart baud-rate clock or timer function. (1) reading the count data, cal culating and setting it to uart communication baud-rate register s, can make more accurate baud-rate clock. (2) reading the count data, cal culating and setting it to a timer data regist er, can make more accurate timing in normal timer mode. figure 9-3 shows the operation timing in frequency measurement mode. figure 9-3 operation timing in frequency measurement mode (1) high-speed clock (hsclk, htbclk) has to be in oscilla ting state by controlling with fconn registers. and also select 1/1 divide ratio of the high-speed time base counter by setting ht bdr (high-speed time base counter divide register) register to 0fh. (2) reset both t2run bit (bit0 of tm2con1 register) and t3run bit (bit0 of tm3con1 register) to ?0? to stop the timer. and then, check both t2stat bit (bit7 of tm2con1 register) and t3stat bit (bit7 of tm3con1 register) are ?0? for making certain the timer stops. (3) set t23mfm bit (bit3 of tm2con0 register) to ?1? (frequency measurement mode), set t23m16 bit (bit2 of tm2con0 register) to ?1? (16bit mode) and set t2cs1-0 b its(bit1/0 of tm2con0 register) to ?01?(htbclk mode). (4) set ?ffh? to both tm2d register and tm3d register. (5) clear both tm2c register and tm3c register to ?00h?. (6) set t2run bit (bit0 of tm2con1 register) to ?1? to start counting the timer. (h) ffff n1 0000 t23mfm t23m16 t2run t2stat tm3int 437c 64hz (3) (5) (6) (7) (8) 437/32768s { tm3c,tm2c}
ml610q407/ml610q408/ml610q409 user's manual chapter 9 timer 9-22 (7) when (t23mfm bit == "1") and (tm23m16 bit == "1") and (t2run bit == "1"), the count up starts with th e falling of the 64hz clock signal. (8) the count-up stops at the falling edge of the next timer clock (ht bclk) after 437c signal becomes ?1?. also, at the same time, t2run bit and t2stat b it become ?0? and the interr upt signal tm3int activates. the 437c signal is the pulse signal that rises in 437/32768 seconds after the falling of the 64hz signal. (9) after checking t2stat bit or tm3int interrupt occurs, read out the data (n1) of tm2c register and tm3c register. for example of utilizing n1, 9600hz timer interrupt is generated. assuming a low-accuracy high-speed clock (htbclk) is exactly 600khz, then the count value n1 is: n1 = 600000 437 / 32768 = 8001 (decimal) = 1f41 (hexadecimal) = 0001 1111 0100 0001 (binary) because 437/32768 seconds are equiva lent to 128 clocks at 9600 hz (more precisely, 9598 hz), dividing the count value ni by 128 provides the fre quency ratio (n2) between the htbclk and 9600 hz. because 128 = 2^7, this calculation can be solved by truncating the right-hand se ven digits of n1 (binary), that is: n2 = 8001(decimal) / 128 (decimal) =0001 1111 0 (binary) =3e (hexadecimal) =62 (decimal) this indicates that 9600hz is about 62 times the cycle of htbclk. therefore, for an operation in the timer mode where the timer data register is set to 3eh ? 1 = 3dh to overflow the counter every 62 counts of the htbclk clock, the tmnint interrupt signal cycle ttmnint is: ttmnint = 1 / 600000 62 = 0.10333ms(9677hz)
ml610q407/ml610q408/ml610q409 user's manual chapter 9 timer 9-23 9.3.3 16-bit timer frequency measurement mode application for setting uart baud-rate for example, when the target baud-rate is 9600bps and the clock is hsclk(500khz), the uart0 baud-rate register (ua0brth, ua0brtl) should be set as: ua0brth, ua0brtl = 500000/9600 ? 1 = 51 (decimal) = 33 (hexadecimal) (see section 14.3.2.) however, actual 500khz rc oscillation clock has temperature variation and production tole rance, the calculation by using the fixed value of 500khz cannot ma ke accurate baud-rate. to compensate it, count the frequency in the frequency measurement mode to set the baud-rate again before operating uart communication. after finishing the clock count in the frequency measur ement mode, assuming htbclk is 451khz, data of tm2c register and tm3c register will be: n1 = 451000 437 / 32768 = 6014 (decimal) = 177e (hexadecimal) = 1011101111110 (binary) as (437 / 32768) sec is equivalent to 128 clocks at 9600hz (more precisely, 9598hz), a division of the count (n1) by 128 equals frequency ratio (n2) between the frequency of htbclk and 9600hz. for the calculation, the accuracy of baud-rate depends on truncating (1) or rounding (2) the data. uart0 baud rate registers h and l are: ua0brth, ua0brtl = (frequency ratio between htbclk cl ock and baud rate) - 1 = (n1/128)-1 = n2 -1 (see section 14.3.2.) ? round data in calculation n1 = 1011101111110 (binary) n2 = 101111 (binary) = 47 (decimal) = 2f (hexadecimal) set n2-1 (= 2e) to ua0brth and ua0brtl registers. in this case, the actual baud-rate will be 9595.744681.. [bps], so the accuracy = ((9595.744681/9600) -1)* 100= -0.04..[%]. ? truncate data in calculation (the accu racy of baud-rate becomes worse) n1 = 1011101111110 (binary) n2 = 101110 (binary) = 46 (decimal) = 2e (hexadecimal) set n2-1 (= 2d) to ua0brth and ua0brtl registers. in this case, the actual baud-rate will be 9804.347826.. [bps], so the accuracy = ((9804.347826/9600) -1)* 100= 2.12..[%]. table 9-5 shows the baud rate and accuracy (theoretical) when the baud rate cloc k is set to 500khz. table 9-6 shows the baud rate and accuracy (theor etical) when the baud rate clock is set to 2mhz. table 9-5 baud rate and accuracy (theoret ical) for baud rate clock set to 500khz baud-rate[bps] data setting to ua0b rth register and ua0brth register theoretical accuracy 300 round off {n1/4 (2bit right-shift) } - (minus) 1. 600 round off {n1/8 (3bit right-shift) } - (minus) 1. 1200 round off {n1/16 (4bit right-shift) } - (minus) 1. 2400 round off {n1/32 (5bit right-shift) } - (minus) 1. 4800 round off {n1/64 (6bit right-shift) } - (minus) 1. 9600 round off {n1/128 (7bit right-shift) } - (minus) 1. ~ 2% 19200 round off {n1/256 (8bit right-shift) } - (minus) 1. 2% ~ 2.5% 38400 round off {n1/512 (9bit right-shift) } - (minus) 1. 2.5% ~
ml610q407/ml610q408/ml610q409 user's manual chapter 9 timer 9-24 table 9-6 baud rate and accuracy (theoret ical) for baud rate clock set to 2mhz baud-rate[bps] data setting to ua0b rth register and ua0brth register theoretical accuracy 300 round off {n1/4 (2bit right-shift) } - (minus) 1. 600 round off {n1/8 (3bit right-shift) } - (minus) 1. 1200 round off {n1/16 (4bit right-shift) } - (minus) 1. 2400 round off {n1/32 (5bit right-shift) } - (minus) 1. 4800 round off {n1/64 (6bit right-shift) } - (minus) 1. 9600 round off {n1/128 (7bit right-shift) } - (minus) 1. 19200 round off {n1/256 (8bit right-shift) } - (minus) 1. 38400 round off {n1/512 (9bit right-shift) } - (minus) 1. ~ 2%
ml610q407/ml610q408/ml610q409 user's manual chapter 9 timer 9-25 9.4 operating timers by external clock inputs when the external clock is selected as the operation clock for the timer 0 (8-bit timer mode), operate it by inputting the clock from the p04 or with the p44 set to the 1st function. when the external clock is selected as the operation clock for the timer 1 (8-bit timer mode), operate it by inputting the clock with the p45 set to the 1st function. when the external clock is selected as the operation clock for the timer 2 (8-b it timer mode), operate it by inputting the clock from the p04 or with the p44 set to the 1st function. when the external clock is selected as the operation clock for the timer 3 (8-bit timer mode), operate it by inputting the clock with the p45 set to the 1st function. when the external clock is selected as the operation clock for the timers 0 and 1 set to the 16-bit timer mode, operate them by inputting the clock from the p04. when the external clock is selected as the operation clock for the timers 2 and 3 set to the 16-bit timer mode, operate them by inputting the clock with the p44 set to the 1st function. set the external clock frequency to a value below the operating frequency (fop) in "appendix c electrical characteristics." 9.4.1 operating timer 0 (8-bit timer mode) by external clock (p04/t02p0ck) select the external clock(p04/t02p0ck) and timer0 (8-bit mode) in the tm0con0 register, and input the operation clock for the timer 0 from the p04 pin. 9.4.2 operating timer 0 (8-bit timer mode) by external clock (p44/t02p0ck) set the p44md1 bit (p4mod1 register's bit 4) to "0" and the p44md0 bit (p4mod0 register's bit 4) to "0" for specifying the p44 to the 1st function. register name p4mod1 register (address: 0f225h) bit 7 6 5 4 3 2 1 0 bit name p47md1 p46md1 p45md1 p44md1 p43md1 p42md1 p41md1 p40md1 setting value * * * 0 * * * * register name p4mod0 register (address: 0f224h) bit 7 6 5 4 3 2 1 0 bit name p47md0 p46md0 p45md0 p44md0 p43md0 p42md0 p41md0 p40md0 setting value * * * 0 * * * * set the p43dir bit (p4dir register's bit 3) to "1" for specifying the state mode of the p44 pin to input. register name p4dir register (address: 0f221h) bit 7 6 5 4 3 2 1 0 bit name p47dir p46dir p45dir p44dir p43dir p42dir p41dir p40dir setting value * * * 1 * * * * select the external clock(p44/t02p0ck) and timer0 (8-bit mode ) in the tm0con0 register, and input the operation clock for the timer 0 from the p44 pin.
ml610q407/ml610q408/ml610q409 user's manual chapter 9 timer 9-26 9.4.3 operating timer 1 (8-bit timer mode) by external clock (p45/t13ck) set the p45md1 bit (p4mod1 register's bit 5) to "0" and the p45md0 bit (p4mod0 register's bit 5) to "0" for specifying the p45 to the 1st function. register name p4mod1 register (address: 0f225h) bit 7 6 5 4 3 2 1 0 bit name p47md1 p46md1 p45md1 p44md1 p43md1 p42md1 p41md1 p40md1 setting value * * 0 * * * * * register name p4mod0 register (address: 0f224h) bit 7 6 5 4 3 2 1 0 bit name p47md0 p46md0 p45md0 p44md0 p43md0 p42md0 p41md0 p40md0 setting value * * 0 * * * * * set the p45dir bit (p4dir register's bit 5) to "1" for specifying the state mode of the p45 pin to input. register name p4dir register (address: 0f221h) bit 7 6 5 4 3 2 1 0 bit name p47dir p46dir p45dir p44dir p43dir p42dir p41dir p40dir setting value * * 1 * * * * * select the external clock(p45/t13p0ck) and timer1 (8-bit mode) in the tm0con0 and tm1con0 register, and input the operation clock for the timer 1 from the p45 pin.
ml610q407/ml610q408/ml610q409 user's manual chapter 9 timer 9-27 9.4.4 operating timer 2 (8-bit timer mode) by external clock (p04/t02p0ck) select the external clock(p04/t02p0ck) and timer2 (8-b it mode) in the tm2con0 register, and input the operation clock for the timer 2 from the p04 pin. 9.4.5 operating timer 2 (8-bit timer mode) by external clock (p44/t02p0ck) set the p44md1 bit (p4mod1 register's bit 4) to "0" and the p44md0 bit (p4mod0 register's bit 4) to "0" for specifying the p44 to the 1st function. register name p4mod1 register (address: 0f225h) bit 7 6 5 4 3 2 1 0 bit name p47md1 p46md1 p45md1 p44md1 p43md1 p42md1 p41md1 p40md1 setting value * * * 0 * * * * register name p4mod0 register (address: 0f224h) bit 7 6 5 4 3 2 1 0 bit name p47md0 p46md0 p45md0 p44md0 p43md0 p42md0 p41md0 p40md0 setting value * * * 0 * * * * set the p44dir bit (p4dir register's bit 4) to "1" for specifying the state mode of the p44 pin to input. register name p4dir register (address: 0f221h) bit 7 6 5 4 3 2 1 0 bit name p47dir p46dir p45dir p44dir p43dir p42dir p41dir p40dir setting value * * * 1 * * * * select the external clock(p44/t02p0ck) and timer2 (8-b it mode) in the tm2con0 register, and input the operation clock for the timer 2 from the p44 pin.
ml610q407/ml610q408/ml610q409 user's manual chapter 9 timer 9-28 9.4.6 operating timer 3 (8-bit timer mode) by external clock (p45/t13ck) set the p45md1 bit (p4mod1 register's bit 5) to "0" and the p45md0 bit (p4mod0 register's bit 5) to "0" for specifying the p45 to the 1st function. register name p4mod1 register (address: 0f225h) bit 7 6 5 4 3 2 1 0 bit name p47md1 p46md1 p45md1 p44md1 p43md1 p42md1 p41md1 p40md1 setting value * * 0 * * * * * register name p4mod0 register (address: 0f224h) bit 7 6 5 4 3 2 1 0 bit name p47md0 p46md0 p45md0 p44md0 p43md0 p42md0 p41md0 p40md0 setting value * * 0 * * * * * set the the p45dir bit (p4dir register's bit 5) to "1" for specifying the state mode of the p45 pin to input. register name p4dir register (address: 0f221h) bit 7 6 5 4 3 2 1 0 bit name p47dir p46dir p45dir p44dir p43dir p42dir p41dir p40dir setting value * * 1 * * * * * select the external clock(p45/t13ck) and timer3 (8-bit m ode) in the tm3con0 register, and input the operation clock for the timer 3 from the p45 pin.
ml610q407/ml610q408/ml610q409 user's manual chapter 9 timer 9-29 9.4.7 operating timer 0 and timer 1 (16-bit tim er mode) by external clock (p04/t02p0ck) select the external clock(p04/t02p0ck) and timers 0 a nd 1 (16-bit mode) in the tm0con0 register, and input the operation clock for the timers 0 and 1 (16-bit mode) from the p04 pin. 9.4.8 operating timer 0 and timer 1 (16-bit tim er mode) by external clock (p44/t02p0ck) set the p44md1 bit (p4mod1 register's bit 4) to "0" and the p44md0 bit (p4mod0 register's bit 4) to "0" for specifying the p44 to the 1st function. register name p4mod1 register (address: 0f225h) bit 7 6 5 4 3 2 1 0 bit name p47md1 p46md1 p45md1 p44md1 p43md1 p42md1 p41md1 p40md1 setting value * * * 0 * * * * register name p4mod0 register (address: 0f224h) bit 7 6 5 4 3 2 1 0 bit name p47md0 p46md0 p45md0 p44md0 p43md0 p42md0 p41md0 p40md0 setting value * * * 0 * * * * set the p43dir bit (p4dir register's bit 3) to "1" for specifying the state mode of the p44 pin to input. register name p4dir register (address: 0f221h) bit 7 6 5 4 3 2 1 0 bit name p47dir p46dir p45dir p44dir p43dir p42dir p41dir p40dir setting value * * * 1 * * * * select the external clock(p44/t02p0ck) and timers 0 a nd 1 (16-bit mode) in the tm0con0 register, and input the operation clock for the timers 0 and 1 (16-bit mode) from the p44 pin.
ml610q407/ml610q408/ml610q409 user's manual chapter 9 timer 9-30 9.4.9 operating timer 2 and timer 3 (16-bit tim er mode) by external clock (p44/t02p0ck) set the p44md1 bit (p4mod1 register's bit 4) to "0" and the p44md0 bit (p4mod0 register's bit 4) to "0" for specifying the p44 to the 1st function. register name p4mod1 register (address: 0f225h) bit 7 6 5 4 3 2 1 0 bit name p47md1 p46md1 p45md1 p44md1 p43md1 p42md1 p41md1 p40md1 setting value * * * 0 * * * * register name p4mod0 register (address: 0f224h) bit 7 6 5 4 3 2 1 0 bit name p47md0 p46md0 p45md0 p44md0 p43md0 p42md0 p41md0 p40md0 setting value * * * 0 * * * * set the p44dir bit (p4dir register's bit 4) to "1" for specifying the state mode of the p44 pin to input. register name p4dir register (address: 0f221h) bit 7 6 5 4 3 2 1 0 bit name p47dir p46dir p45dir p44dir p43dir p42dir p41dir p40dir setting value * * * 1 * * * * select the external clock(p44/t02p0ck) and timers 2 a nd 3 (16-bit mode) in the tm2con0 register, and input the operation clock for the timers 2 and 3 (16-bit mode) from the p44 pin.
chapter 10 pwm
ml610q407/ml610q408/ml610q409 user's manual chapter 10 pwm 10-1 10. pwm 10.1 overview this lsi includes one channel of 16-bit pwm (pulse width modulation). the pwm output (pwm0) is assigned to the tertiary function of the p43 (port 4) or the secondary function of the p24 (port 2). for the functions of port 4 and port 2, see chapter 17, ?port 4? and chapter 15, ?port 2?. 10.1.1 features ? capable of generating and externally outputting a pwm signal at a cycle ranging from 2000ns (@htbclk = 500khz) to 2s (@lsclk = 32.768khz)(*) ? the output logic of the pwm signal can be switched to the positive or negative logic. ? at the coincidence of pwm signal period, duties, and period & duty, a pwm interrupt (pw0int) occurs. ? for the pwm clock, a low-speed clock (lsclk), a high- speed time base clock (htbclk), and an external clock are available. (*) for hsclk 2mhz, the cycle ranges from 500ns (@htbclk=2mhz) to 2s (@lsclk=32.768khz). 10.1.2 configuration figure 10 - 1 shows the configuration of the pwm circuit. pw0pl : pwm0 period register l pw0ph : pwm0 period register h pw0pbuf : pwm0 period buffer pw0dl : pwm0 duty register l pw0dh : pwm0 duty register h pw0dbuf : pwm0 duty buffer pw0cl : pwm0 counter register l pw0ch : pwm0 counter register h pw0con0 : pwm0 control register 0 pw0con1 : pwm0 control register 1 figure 10-1 configuration of pwm circuit pw0ch/l 16 data bus pw0int lsclk pw0con0 pw0con1 r cycle matched comparator htbclk external clock p04/t02p0ck p44/t02p0ck write pw0cl p0ck write pw0ch comparator output control circuit p43/pwm0 p24/pwm0 p0neg duty matched p0flg 16 16 8 8 8 8 8 8 pw0pbuf pw0dbuf pw0ph/l pw0dh/l pw0ch latch read pw0cl
ml610q407/ml610q408/ml610q409 user's manual chapter 10 pwm 10-2 10.1.3 list of pins pin name input/output function p04/t02p0ck i pwm0 external clock input pin used for the primary func tion of the p04 pin. p44/t02p0ck i pwm0 external clock input pin used for the primary func tion of the p44 pin. p43/pwm0 o pwm0 output pin used for the tertiary f unction of the p43 pin. p24/pwm0 o pwm0 output pin used as the secondary func tion of the p24 pin. 10.2 description of registers 10.2.1 list of registers address name symbol (byte) symbol (word) r/w size initial value 0f0a0h pwm0 period register l pw0pl r/w 8/16 0ffh 0f0a1h pwm0 period register h pw0ph pw0p r/w 8 0ffh 0f0a2h pwm0 duty register l pw0dl r/w 8/16 00h 0f0a3h pwm0 duty register h pw0dh pw0d r/w 8 00h 0f0a4h pwm0 counter regi ster l pw0cl r/w 8/16 00h 0f0a5h pwm0 counter register h pw0ch pw0c r/w 8 00h 0f0a6h pwm0 control register 0 pw0con0 r/w 8/16 00h 0f0a7h pwm0 control register 1 pw0con1 pw0con r/w 8 40h
ml610q407/ml610q408/ml610q409 user's manual chapter 10 pwm 10-3 10.2.2 pwm0 period registers (pw0pl, pw0ph) address: 0f0a0h access: r/w access size: 8-bit initial value: 0ffh 7 6 5 4 3 2 1 0 pw0pl p0p7 p0p6 p0p5 p0p4 p0p3 p0p2 p0p1 p0p0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 1 1 1 1 1 1 1 1 address: 0f0a1h access: r/w access size: 8-bit initial value: 0ffh 7 6 5 4 3 2 1 0 pw0ph p0p15 p0p14 p0p13 p0p12 p0p11 p0p10 p0p9 p0p8 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 1 1 1 1 1 1 1 1 pw0ph and pw0pl are special function registers (sfrs) to set the pwm0 periods. note: when pw0ph or pw0pl is set to ?0000h?, the pwm0 period buffer (pw0pbuf) is set to ?0001h?.
ml610q407/ml610q408/ml610q409 user's manual chapter 10 pwm 10-4 10.2.3 pwm0 duty registers (pw0dl, pw0dh) 7 6 5 4 3 2 1 0 pw0dl p0d7 p0d6 p0d5 p0d4 p0d3 p0d2 p0d1 p0d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 address: 0f0a2h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 pw0dh p0d15 p0d14 p0d13 p0d12 p0d11 p0d10 p0d9 p0d8 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 address: 0f0a3h access: r/w access size: 8-bit initial value: 00h pw0dh and pw0dl are special function registers (sfrs) to set the duties of pwm0. note: for the pw0dh and pw0dl, set data smaller than for the pw0ph and pw0pl.
ml610q407/ml610q408/ml610q409 user's manual chapter 10 pwm 10-5 10.2.4 pwm0 counter registers (pw0ch, pw0cl) 7 6 5 4 3 2 1 0 pw0cl p0c7 p0c6 p0c5 p0c4 p0c3 p0c2 p0c1 p0c0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 address: 0f0a4h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 pw0ch p0c15 p0c14 p0c13 p0c12 p0c11 p0c10 p0c9 p0c8 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 address: 0f0a5h access: r/w access size: 8-bit initial value: 00h pw0cl and pw0ch are special function registers (sfrs) that function as 16-bit binary counters. when data is written to either pw0cl or pw0ch, pw0cl a nd pw0ch is set to ?0000h?. the data that is written is meaningless. when data is read from pw0cl, the value of pw0ch is latched. when reading pw0ch and pw0cl, use a word type instruction or pre-read pw0cl. the contents of pw0ch and pw0cl during pwm operation ca nnot be read depending on the combination of the pwm clock and system clock. table 10-1 shows pw0ch and pw0cl read enable/disable fo r each combination of the pwm clock and system clock. table 10-1 pw0ch and pw0cl read enable/disable during pwm0 operation pwm clock p0ck system clock sysclk pw0ch and pw0cl read enable/disable lsclk lsclk read enabled. lsclk hsclk read enabled. however, to prev ent the reading of undefined data during counting, read consecut ively pw0ch or pw0cl twice until the last data coinci des the previous data. htbclk lsclk read disabled. htbclk hsclk read enabled. lsclk external clock hsclk read disabled.
ml610q407/ml610q408/ml610q409 user's manual chapter 10 pwm 10-6 10.2.5 pwm0 control register 0 (pw0con0) 7 6 5 4 3 2 1 0 pw0con0 ? ? ? p0neg p0is1 p0is0 p0cs1 p0cs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 address: 0f0a6h access: r/w access size: 8-bit initial value: 00h pw0con0 is a special function register (sfr) to control pwm. [description of bits] ? p0cs1, p0cs0 (bits 1, 0) the p0cs1 and p0cs0 bits are used to select the pwm0 operation clocks. lsclk, htbclk, or the external clock (p44/t02p0ck) can be se lected by these bits. p0cs1 p0cs0 description 0 0 lsclk (initial value) 0 1 htbclk 1 0 external clock (p04/t02p0ck) 1 1 external clock (p44/t02p0ck) ? p0is1, p0is0 (bits 3, 2) the p0is1 and p0is0 bits are used to select the point at wh ich the pwm0 interrupt occurs. ?when the periods coincide?, ?when the duties coincide?, or ?when the pe riods and duties coincide? can be selected. p0is1 p0is0 description 0 0 when the periods coincide. (initial value) 0 1 when the duties coincide. 1 * when the periods and duties coincide. ? p0neg (bit 4) the p0neg bit is used to select the output logic. when the positive logic is selected, the initial value of pwm0 output is ?1?, and when the negative logic is selected, the initial value of pwm0 output is ?0?. p0neg description 0 positive logic (initial value) 1 negative logic
ml610q407/ml610q408/ml610q409 user's manual chapter 10 pwm 10-7 10.2.6 pwm0 control register 1 (pw0con1) 7 6 5 4 3 2 1 0 pw0con1 p0stat p0flg ? ? ? ? ? p0run r/w r r/w r/w r/w r/w r/w r/w r/w initial value 0 1 0 0 0 0 0 0 address: 0f0a7h access: r/w access size: 8-bit initial value: 40h pw0con1 is a special function register (sfr) to control pwm0. [description of bits] ? p0run (bit 0) the p0run bit is used to control count stop/start of pwm0. p0run description 0 stops counting. (initial value) 1 starts counting. ? p0flg (bit 6) the p0flg bit is used to r ead the output flag of pwm0. this bit is set to ?1? when write operation to pw0ch or pw0cl is performed. p0flg description 0 pwm0 output flag = ?0? 1 pwm0 output flag = ?1? (initial value) ? p0stat (bit 7) the p0stat bit indicates ?counting stopped or ?counting in progress? of pwm0. p0stat description 0 counting stopped. (initial value) 1 counting in progress.
ml610q407/ml610q408/ml610q409 user's manual chapter 10 pwm 10-8 10.3 description of operation the pwm0 counter registers (pw0ch, pw0cl) are set to an operating state (p0stat is set to ?1?) on the first falling edge of the pwm clock (p0ck) that ar e selected by the pwm0 control regist er 0 (pw0con0) when the p0run bit of pwm0 control register 1 (pw0con1) is set to ?1? and increment the count value on the 2nd falling edge. when the count value of pwm0 counter registers and the value of the pwm0 duty buffer (pw0dbuf) coincide, the pwm flag (p0flg) is set to ?0? on the next timer clock falling edge of p0ck. when the pw0ch and pw0cl count values match the pwm0 period buffer value, the p0flg becomes "1" at the next p0ck falling edge and the pw0ch and pw0cl are reset to 0000h to continue incremental counting. at the same time, the value of the pwm0 duty register (pw0dh, pw0dl) is transferred to the pwm0 duty buffer (pw0dbuf) and the value of pwm0 period register (pw0ph, pw0pl) to the pwm0 period buffer (pw0pbuf). when the p0run bit is set to ?0?, pwm0 counter registers st op counting after counting once the falling of the pwm clock (p0ck). confirm that pw0ch and pw0cl are stopped by checking that the pnstat bit of the pwm0 control register 1 (pw0con1) is ?0?. when the p0run bit is set to ?1? again, pwm0 counter registers restarts incremental counting from the previous value on the falling edge of p0ck. to initialize pwm0 counter registers to ?0000h?, perform write operation in either of pw0ch or pw0cl. at that time, p0flg is also set to ?1?. when data is written in the pwm0 duty register (pw0dh, pw0dl) during count stop (p0r un is in a ?1? state), the data is transferred to the pwm0 duty buffer (pw0dbuf) and when data is written in the pwm0 period register (pw0ph, pw0pl), the data is transferred to the pwm0 period buffer (pw0pbuf). the pwm clock, the point at which an interrupt of pwm0 occurs, and the logic of the pwm output are selected by pwm0 control register 0 (pw0cn0). the period of the pwm0 signal (t pwp ) and the first half duration (t pwd ) of the duty are expressed by the following equations. pw0p + 1 t pwp = p0ck (hz) pw0d + 1 t pwp = p0ck (hz) pw0p: pwm0 period registers (pw0ph, pw0pl) setting value (0001h to 0ffffh) pw0d: pwm0 duty registers (pw0dh, pw 0dl) setting value (0000h to 0fffeh) p0ck: clock frequency selected by the pw m0 control register 0 (pw0con0)
ml610q407/ml610q408/ml610q409 user's manual chapter 10 pwm 10-9 after the p0run bit is set to ?1?, counting starts in synchronization with the pwm clock. this causes an error of up to 1 clock pulse to the time the first pwm interrupt is issued. the pwm interrupt period from the second time is fixed. figure 10-2 shows the operation timing of pwm0. figure 10-2 (1/2) operation timing diagram of pwm0 figure 10-2 (2/2) operation timing diagram of pwm0 note: even if ?0? is written to the p0run b it, counting operation continues up to the falling edge (the pwm0 status flag (p0stat) is in a ?1? state) of the next pwm clock pul se. therefore, the pwm0 inte rrupt (pw0int) may occur. pw0ch/l xxxx 0000 8000 pw0dh/l pw0int p0stat write pw0ch write pw0cl p0ck p0run 0001 0002 7fff 8000 8001 a000 a000 0000 0001 7777 7777 a000 pw0ph/l bbbb t pwd t pwp p0flg pwm0* (negative logic) 8002 bbbb pw0dbuf pw0pbuf 8000 8000 7777 7777 a000 a000 bbbb bbbb 8000 a000 pw0ch/l p0stat p0ck p0run 2000 2001 2002 2003 2005 2007 2008 2006 p0flg 2004 pwm0* (positive logic)
ml610q407/ml610q408/ml610q409 user's manual chapter 10 pwm 10-10 10.4 specifying port registers to output the pwm waveform, the applicable bit of each related port register needs to be set. see chapter 17, ?port 4? and chapter 15, ?port 2? for detail about the port registers. 10.4.1 functioning the p43 pin (pwm0) as the pwm output set p43md1 bit (bit3 of p4mod1 register) to ?1? and set p43md0 bit (bit3 of p4mod0 register) to ?0?, for specifying the pwm output as the tertiary function of p43. register name p4mod1 register (address: 0f225h) bit 7 6 5 4 3 2 1 0 bit name p47md1 p46md1 p45md1 p44md1 p43md1 p42md1 p41md1 p40md1 setting value * * * * 1 * * * register name p4mod0 register (address: 0f224h) bit 7 6 5 4 3 2 1 0 bit name p47md0 p46md0 p45md0 p44md0 p43md0 p42md0 p41md0 p40md0 setting value * * * * 0 * * * set the p43c1 bit (p4con1 register bit 3) to "1", the p43c0 bit (p4con0 register bit 3) to "1", and the p43dir bit (p4dir register bit 3) to "0" for selecting the state mode of the p43 pin used for the pwm to cmos output. register name p4con1 register (address: 0f223h) bit 7 6 5 4 3 2 1 0 bit name p47c1 p46c1 p45c1 p44c1 p43c1 p42c1 p41c1 p40c1 setting value * * * * 1 * * * register name p4con0 register (address: 0f222h) bit 7 6 5 4 3 2 1 0 bit name p47c0 p46c0 p45c0 p44c0 p43c0 p42c0 p41c0 p40c0 setting value * * * * 1 * * * register name p4dir regi ster (address: 0f221h) bit 7 6 5 4 3 2 1 0 bit name p47dir p46dir p45dir p44dir p43dir p42dir p41dir p40dir setting value * * * * 0 * * * the p43d bit (p4d register bit 3) data can either be "0" or "1". register name p4d register (address: 0f220h) bit 7 6 5 4 3 2 1 0 bit name p47d p46d p45d p44d p43d p42d p41d p40d setting value * * * * ** * * * * : bit not related to the pwm function ** : don?t care
ml610q407/ml610q408/ml610q409 user's manual chapter 10 pwm 10-11 10.4.2 functioning the p24 pin (pwm0) as the pwm output set the p24md bit (p2mod register bit 4) to "1" for specifying the pwm as the secondary function of the p24. register name p2mod register (address: 0f214h) bit 7 6 5 4 3 2 1 0 bit name - - - p24md - p22md p21md p20md setting value - - - 1 * * * * set the p24c1 bit (p2con1 register's bit 4) to "1" and the p24c0 bit (p2con0 register's bit 4) to "1" for specifying the state mode of the p24 pin used for the pwm to cmos output. register name p2con1 register (address: 0f213h) bit 7 6 5 4 3 2 1 0 bit name - - - p24c1 - p22c1 p21c1 p20c1 setting value - - - 1 * * * * register name p2con0 register (address: 0f212h) bit 7 6 5 4 3 2 1 0 bit name - - - p24c0 - p22c0 p21c0 p20c0 setting value - - - 1 * * * * the p24d bit (p2d register bit 4) data can either be "0" or "1". register name p2d register (address: 0f210h) bit 7 6 5 4 3 2 1 0 bit name - - - p24d - p22d p21d p20d setting value - - - ** * * * * - : bit that does not exist * : bit not related to the pwm function ** : don?t care
ml610q407/ml610q408/ml610q409 user's manual chapter 10 pwm 10-12 10.4.3 operating pwm0 with external clock (p04/t02p0ck) set the p04e0 bit (exicon0 register's bit 4) to "0" and the p04e1 bit (exicon1 register's bit 4) to "0" for specifying the p04 external interrupt to disable. register name exicon0 register (address: 0f020h) bit 7 6 5 4 3 2 1 0 bit name - - - p04e0 p03e0 p02e0 p01e0 p00e0 setting value * * * 0 * * * * register name exicon1 register (address: 0f021h) bit 7 6 5 4 3 2 1 0 bit name - - - p04e1 p03e1 p02e1 p01e1 p00e1 setting value * * * 0 * * * * set the p04c0 bit (p0con0 register's bit 4) to "0" and the p04c1 bit (p0con1 register's bit 4) to "0" for specifying the state mode of the p04 pin to high-impedance input. register name p0con0 register (address: 0f206h) bit 7 6 5 4 3 2 1 0 bit name - - - p04c0 p03c0 p02c0 p01c0 p00c0 setting value * * * 0 * * * * register name p0con1 register (address: 0f207h) bit 7 6 5 4 3 2 1 0 bit name - - - p04c1 p03c1 p02c1 p01c1 p00c1 setting value * * * 0 * * * * set the p0cs1 bit (pw0con0 register's bit 1) to "1" and the p0cs0 bit (pw0con0 register's bit 0) to "0". register name tm0con0 register (address: 0f032h) bit 7 6 5 4 3 2 1 0 bit name ? ? ? p0neg pois1 p0is0 p0cs1 p0cs0 setting value * * * * * * 1 0 input the operation clock for the pwm0 from the p04 pin.
ml610q407/ml610q408/ml610q409 user's manual chapter 10 pwm 10-13 10.4.4 operating pwm0 with external clock (p44/t02p0ck) set the p44md1 bit (p4mod1 register's bit 4) to "0" and the p44md0 bit (p4mod0 register's bit 4) to "0" for specifying the p44 to the primary function. register name p4mod1 register (address: 0f225h) bit 7 6 5 4 3 2 1 0 bit name p47md1 p46md1 p45md1 p44md1 p43md1 p42md1 p41md1 p40md1 setting value * * * 0 * * * * register name p4mod0 register (address: 0f224h) bit 7 6 5 4 3 2 1 0 bit name p47md0 p46md0 p45md0 p44md0 p43md0 p42md0 p41md0 p40md0 setting value * * * 0 * * * * set the p44c1 bit (p4con1 register's bit 4) to "0", the p44c0 bit (p4con0 register's bit 4) to "0", and the p43dir bit (p4dir register's bit 3) to "1" for specifying the state mode of the p44 pin to high-impedance input. register name p4con1 register (address: 0f223h) bit 7 6 5 4 3 2 1 0 bit name p47c1 p46c1 p45c1 p44c1 p43c1 p42c1 p41c1 p40c1 setting value * * * 0 * * * * register name p4con0 register (address: 0f222h) bit 7 6 5 4 3 2 1 0 bit name p47c0 p46c0 p45c0 p44c0 p43c0 p42c0 p41c0 p40c0 setting value * * * 0 * * * * register name p4dir regi ster (address: 0f221h) bit 7 6 5 4 3 2 1 0 bit name p47dir p46dir p45dir p44dir p43dir p42dir p41dir p40dir setting value * * * 1 * * * * set the p0cs1 bit (pw0con0 register's bit 1) to "1" and the p0cs0 bit (pw0con0 register's bit 0) to "1". register name tm0con0 register (address: 0f032h) bit 7 6 5 4 3 2 1 0 bit name ? ? ? p0neg pois1 p0is0 p0cs1 p0cs0 setting value * * * * * * 1 1 input the operation clock for the pwm0 from the p44 pin.
chapter 11 watchdog timer
ml610q407/ml610q408/ml610q409 user's manual chapter 11 watchdog timer 11-1 11. watchdog timer 11.1 overview this lsi incorporates a watchdog timer (wdt) that operate s at a system reset unconditi onally (free-run operation) in order to detect an undefined state of the mcu and return from that state. if the wdt counter overflows due to the failure of clearing of the wdt counter within the wdt overflow period, the watchdog timer requests a wdt interrupt (non-maskable interrupt). when the second overflow occurs, the watchdog timer generates a wdt reset signal and shifts the mode to a system reset mode. for interrupts see chapter 5, ?interrupt,? and for wdt interrupt see chapter 3, ?reset function?. 11.1.1 features ? non-maskable interrupt ? free running (cannot be stopped) ? one of four types of overflow periods (125m s, 500ms, 2s, and 8s) selectable by software ? reset generated by the second overflow 11.1.2 configuration figure 11-1 shows the configuration of the watchdog timer. wdtcon : watchdog timer control register wdtmod : watchdog timer mode register figure 11-1 configuration of watchdog timer data bus wdp dq r qn ?5ah? perform detection ?0a5h? perform detection wdt counter r reset interrupt control wdt reset wdtint non-maskable interrupt reset_s s y stem reset t256hz wdtcon write wdt overflow wdtmod wdtcon
ml610q407/ml610q408/ml610q409 user's manual chapter 11 watchdog timer 11-2 11.2 description of registers 11.2.1 list of registers address name symbol (byte) symbol (word) r/w size initial value 0f00eh watchdog timer control register wdtcon ? r/w 8 00h 0f00fh watchdog timer mode register wdtmod ? r/w 8 02h
ml610q407/ml610q408/ml610q409 user's manual chapter 11 watchdog timer 11-3 11.2.2 watchdog timer control register (wdtcon) address: 0f00eh access: w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 wdtcon d7 d6 d5 d4 d3 d2 d1 wdp/d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 wdtcon is a special function register (sfr) to clear the wdt counter. when wdtcon is read, the value of the inte rnal pointer (wdp) is read from bit 0. [description of bits] ? wdp/d0 (bit 0) the value of the internal pointer (wdp) is read from this bit. the wdp is reset to ?0? at the system reset or wdt counter overflow and is inverted every writing to wdtcon. ? d7-d0 (bits 7-0) this bit is used to write data to clear the wdt count er. the wdt counter can be cleared by writing "5ah" with the internal pointer (wdp) is "0", then writing "0a5h" with the wdp "1". note: when the wdt interrupt (wdtint) occurs by the first wdt counter overflow, the counter and the internal pointer (wdp) are initialiaed for a half cycle of low speed clock (about 15us). during th e time period that they are initialized, writing to wdtcon is disable and the logic of wdp does not change. therefore, in the case of that you have program codes handle to clear the wdt when the first overflow wdt interrupt occurs and also the codes run at high-speed system clock, please check the wdp gets reve rsed after writing to wdtcon to see if the writing was surely successful. for example of the program code, see section 11.3.1, "handling example when you do not want to use the watch dog timer".
ml610q407/ml610q408/ml610q409 user's manual chapter 11 watchdog timer 11-4 11.2.3 watchdog timer mode register (wdtmod) address: 0f00fh access: w access size: 8-bit initial value: 02h 7 6 5 4 3 2 1 0 wdtmod ? ? ? ? ? ? wdt1 wdt0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 1 0 wdtmod is a special function register to set the overflow period of the wdt counter. [description of bits] ? wdt1-0 (bits 1-0) these bits are used to select an overflow period of the watchdog timer. the wdt1 and wdt0 bits set an overflow period (t wov ) of the wdt counter. one of 125ms, 500ms, 2s, and 8s can be selected. wdt1 wdt0 description 0 0 125ms 0 1 500ms 1 0 2s (initial value) 1 1 8s
ml610q407/ml610q408/ml610q409 user's manual chapter 11 watchdog timer 11-5 11.3 description of operation the wdt counter starts counting after th e system reset has been released and the low-speed clock oscillation start.. the wdt counter can be cleared by writi ng "5ah" with the internal pointer (wdp ) is "0", then writing "0a5h" with the wdp "1". the wdp is reset to ?0? at the system reset or wdt c ounter overflow and is invert ed every writing to wdtcon. when the wdt counter cannot be cleared within the wdt counter overflow period (t wov ), a watchdog timer interrupt (wdtint) occurs. if the wdt counter is not cleared even by the software processing performed following the watchdog timer interrupt and overflow occurs again, wdt rese t occurs and the mode shifts to a system reset mode. for the overflow period (t wov ) of the wdt counter, one of 125ms, 500ms, 2s, and 8s can be selected by the watchdog mode register (wdtmod). clear the wdt counter within the clear period of the wdt counter (t wcl ) shown in table 11-1. table 11-1 clear period of wdt counter wdt1 wdt0 t wov t wcl 0 0 125ms approxi. 121ms 0 1 500ms approx. 496 ms 1 0 2000ms approx. 1996 ms 1 1 8000ms approx. 7996 ms
ml610q407/ml610q408/ml610q409 user's manual chapter 11 watchdog timer 11-6 figure 11-2 shows an example of watchdog timer operation. figure 11-2 example of watchdog timer operation ? the wdt counter starts counting after the system reset has been released and the low-speed clock oscillation start. ? the overflow period of the wdt counter (t wov ) is set to wdtmod. ? ?5ah? is written to wdtcon. (internal pointer 0 to 1) ? ?0a5h? is written to wdtcon and the wdt count er is cleared. (internal pointer 1 to 0) ? ?5ah? is written to wdtcon. (internal pointer 0 to 1) ? when ?5ah? is written to wdtcon after the occurrence of abnormality, it cannot be accepted as the internal pointer is set to ?1?. (internal pointer 1 to 0) ? although ?0a5h? is written to wdtcon, the wdt counter is not cleared since the internal pointer is ?0? and the writing of ?5ah? is not accepted in h . (internal pointer 0 to 1) ? the wdt counter overflows and a watchdog timer interrupt re quest (wdtint) is generated. in this case, the wdt counter and the internal pointer (wdp) are initialiaed for a half cycle of low speed clock (about 15.26us). ? if the wdt counter is not cleared even by the software processing performed following a watchdog timer interrupt and the wdt counter overflows again, wdt reset occurs and the mode is shifted to a system reset mode. note: k in stop mode, the watchdog timer operation also stops. k in halt mode, the watchdog timer operation does not stop. when the wdt interrupt occurs, the halt mode is released. k the watchdog timer cannot detect all the abnormal operations . even if the cpu loses control, the watchdog timer cannot detect the abnormality in the operation state in which the wdt counter is cleared. e 5a f a5 g 5a h 5a occurrence of abnormality i a5 t wov overflow period overflow low-speed clock oscillation program start 5a a5 data: reset_s system reset wdtcon write wdtp internal pointer wdt counter wdtint wdt interrupt wdt reset t wov overflow period d wdtmod setting wdtmod setting j occurrence of wdtint k occurrence of wdt reset
ml610q407/ml610q408/ml610q409 user's manual chapter 11 watchdog timer 11-7 11.3.1 handling example when you do not want to use the watch dog timer wdt counter is a free-run counter that starts count-up automatically after the system reset released and the low-speed clock (lsclk) starts oscillating. if the wdt counter gets overflow, the wdt non-ma skable interrupt occurs and then a system reset occurs. therefore, it is needed to clear the wdt counter even if you do not want to use the wdt as a fale-safe function. see following example programming codes to clear the wdt counter in the interrupt routine. example programming code: __di(); // disable multi-interrupts do { wdtcon = 0x5a; } while(wdp != 1) wdtcon = 0xa5; __ei();
chapter 12 synchronous serial port
ml610q407/ml610q408/ml610q409 user's manual chapter 12 synchronous serial port 12-1 12 synchronous serial port 12.1 overview this lsi includes two channels of 8/16-bit synchronous serial ports (ssio). it can also be used to control the device incorporated with the spi interface by using one gpio as the chip enable pin. when the synchronous serial port is used, the tertiary functions of port 4 or the tertiary functions of port 5 must be set. for the tertiary function setting of port 4, see chapter 17, "port 4." for the tertiary function setting of port 5, see chapter 18, "port 5." 12.1.1 features ? master or slave selectable ? msb first or lsb first selectable ? 8-bit length or 16-bit length selectable fro the data length 12.1.2 configuration figure 12-1 shows the configuration of the synchronous serial port. shift register 8bits/16bits data bus send register sio1trh,l control circuit sio1con sio1mod0 sio1mod1 p51/sck1 receive register sio1rch,l lsb/msb control sio1bufh, sio1bufl 1/4 hsclk to 1/64 hsclk t32khz to t128hz p50/sin1 p54/sin1 p51/sck1 p55/sck1 p52/sout1 p56/sout1 sio1int tbc synchronous serial port 1 ssio1 p55/sck1 shift register 8bits/16bits data bus send register sio0trh,l control circuit sio0con sio0mod0 sio0mod1 p41/sck0 p45/sck0 receive register sio0rch,l lsb/msb control sio0bufh, sio0bufl 1/4 hsclk to 1/64 hsclk t32khz to t128hz p40/sin0 p44/sin0 p41/sck0 p45/sck0 p42/sout0 p46/sout0 sio0int tbc synchronous serial port 0 (ssio0)
ml610q407/ml610q408/ml610q409 user's manual chapter 12 synchronous serial port 12-2 sio0bufl, sio1bufl : serial port transmit/receive buffer l sio0bufh, sio1bufh : serial port transmit/receive buffer h sio0con, sio1con : serial port control register sio0mod0, sio1mod0 : serial port mode register 0 sio0mod1, sio1mod1 : serial port mode register 1 figure 12-1 configuration of synchronous serial port 12.1.3 list of pins pin name i/o function p40/sin0 p44/sin0 i received data input. used for the tertiary functi on of the p40 and p44 pins. p41/sck0 p45/sck0 i/o synchronous clock input/output. used for the tertiary functi on of the p41 and p45 pins. p42/sout0 p46/sout0 o transmitted data output. used for the tertiary functi on of the p42 and p46 pins. p50/sin1 p54/sin1 i received data input. used for the secondary function of the p50 pin and p54 pin. p51/sck1 p55/sck1 i/o synchronous clock input/output. used for the secondary function of the p51 pin and p55 pin. p52/sout1 p56/sout1 o transmitted data output. used for the secondary function of the p52 pin and p56 pin. 12.2 description of registers 12.2.1 list of registers address name symbol (byte) symbol (word) r/w size initial value 0f280h serial port 0 transmit/receive buffer l sio0bufl r/w 8/16 00h 0f281h serial port 0 transmit/receive buffer h sio0bufh sio0buf r/w 8 00h 0f282h serial port 0 control r egister sio0con ? r/w 8 00h 0f284h serial port 0 mode regist er 0 sio0mod0 r/w 8/16 00h 0f285h serial port 0 mode register 1 sio0mod1 sio0mod r/w 8 00h 0f288h serial port 1 transmit/receive buffer l sio1bufl r/w 8/16 00h 0f289h serial port 1 transmit/receive buffer h sio1bufh sio1buf r/w 8 00h 0f28ah serial port 1 control r egister sio1con ? r/w 8 00h 0f28ch serial port 1 mode regist er 0 sio1mod0 r/w 8/16 00h 0f28dh serial port 1 mode register 1 sio1mod1 sio1mod r/w 8 00h
ml610q407/ml610q408/ml610q409 user's manual chapter 12 synchronous serial port 12-3 12.2.2 serial port 0 transmit/receive buffers (sio0bufl and sio0bufh) address: 0f280h access: r/w access size: 8 bits/16 bits initial value: 00h 7 6 5 4 3 2 1 0 sio0bufl s0b7 s0b6 s0b5 s0b4 s0b3 s0b2 s0b1 s0b0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 address: 0f281h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 sio0bufh s0b15 s0b14 s0b13 s0b12 s0b11 s0b10 s0b9 s0b8 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 sio0bufl and sio0bufh are special func tion registers (sfrs) to write transmitte d data and to read received data of the synchronous serial port 0. when data is written in sio0bufl and sio0bufh, the da ta is written in the transmit registers (sio0trl and sio0trh). when data is read from sio0bufl and sio0bufh , the contents of the receive registers (sio0rcl and sio0rch) are read.
ml610q407/ml610q408/ml610q409 user's manual chapter 12 synchronous serial port 12-4 12.2.3 serial port 1 transmit/receive buffers (sio1bufl and sio1bufh) address: 0f288h access: r/w access size: 8 bits/16 bits initial value: 00h 7 6 5 4 3 2 1 0 sio1bufl s1b7 s1b6 s1b5 s1b4 s1b3 s1b2 s1b1 s1b0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 address: 0f289h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 sio1bufh s1b15 s1b14 s1b13 s1b12 s1b11 s1b10 s1b9 s1b8 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 sio1bufl and sio1bufh are special func tion registers (sfrs) to write transmitte d data and to read received data of the synchronous serial port 1. when data is written in sio1bufl and sio1bufh, the da ta is written in the transmit registers (sio1trl and sio1trh). when data is read from sio1bufl and sio1bufh , the contents of the receive registers (sio1rcl and sio1rch) are read.
ml610q407/ml610q408/ml610q409 user's manual chapter 12 synchronous serial port 12-5 12.2.4 serial port 0 control register (sio0con) address: 0f282h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 sio0con ? ? ? ? ? ? ? s0en r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 sio0con is a special function register (sfr) to control the synchronous serial port 0. [description of bits] ? s0en (bit 0) the s0en bit is used to specify start of synchronous serial communica tion. writing a ?1? to s0en starts 8-/16-bit data communication. the s0en bit is set to ?0? automatically when 8-/16-bit data communication is terminated. the s0en bit is set to ?0? at a system reset. s0en description 0 stops communication. (initial value) 1 starts communication 12.2.5 serial port 1 control register (sio1con) address: 0f28ah access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 sio1con ? ? ? ? ? ? ? s1en r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 sio1con is a special function register (sfr) to control the synchronous serial port 1. [description of bits] ? s1en (bit 0) the s1en bit is used to specify start of synchronous serial communica tion. writing a ?1? to s1en starts 8-/16-bit data communication. the s1en bit is set to ?0? automatically when 8-/16-bit data communication is terminated. the s1en bit is set to ?0? at a system reset. s1en description 0 stops communication. (initial value) 1 starts communication
ml610q407/ml610q408/ml610q409 user's manual chapter 12 synchronous serial port 12-6 12.2.6 serial port 0 mode register 0 (sio0mod0) address: 0f284h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 sio0mod0 ? ? ? ? s0lg s0md1 s0md0 s0dir r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 sio0mod0 is a special function register (sfr) to set mode of the synchronous serial port 0. [description of bits] ? s0dir (bit 0) s0dir is the bit for selecting lsb first or msb first. s0dir description 0 lsb first (initial value) 1 msb first ? s0md1 and s0md0 (bits 2 and 1) the s0md1 and s0md0 bits are used to select the transmit/receive mode of the synchronous serial port 0. the receive mode, transmit mode, or tr ansmit/receive mode is selectable. s0md1 s0md0 description 0 0 stops transmission/reception (initial value) 0 1 receive mode 1 0 transmit mode 1 1 transmit/receive mode ? s0lg (bit 3) s0lg is the bit that specifi es the transmit/receive buffer bit length. e ither 8-bit length or 16-bit length can be selected. the s0lg bit is set to ?0? at a system reset. s0lg description 0 8-bit length (initial value) 1 16-bit length note: ?do not change any of the sio0mod0 regi ster settings during tr ansmission/reception. ?when the synchronous serial port 0 is used, the tertiary functi ons of port 4 must be set. for the tertiary functions of port 4, see chapter 17, ?port 4?.
ml610q407/ml610q408/ml610q409 user's manual chapter 12 synchronous serial port 12-7 12.2.7 serial port 1 mode register 0 (sio1mod0) address: 0f28ch access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 sio1mod0 ? ? ? ? s1lg s1md1 s1md0 s1dir r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 sio1mod0 is a special function register (sfr) to set mode of the synchronous serial port 1. [description of bits] ? s1dir (bit 0) s1dir is the bit for selecting lsb first or msb first. s1dir description 0 lsb first (initial value) 1 msb first ? s1md1 and s1md0 (bits 2 and 1) the s1md1 and s1md0 bits are used to select the transmit/receive mode of the synchronous serial port 1. the receive mode, transmit mode, or tr ansmit/receive mode is selectable. s1md1 s1md0 description 0 0 stops transmission/reception (initial value) 0 1 receive mode 1 0 transmit mode 1 1 transmit/receive mode ? s1lg (bit 3) s1lg is the bit that specifi es the transmit/receive buffer bit length. e ither 8-bit length or 16-bit length can be selected. the s1lg bit is set to ?0? at a system reset. s1lg description 0 8-bit length (initial value) 1 16-bit length note: ?do not change any of the sio1mod0 regi ster settings during tr ansmission/reception. ?when the synchronous serial port 1 is used, the tertiary functi ons of port 5 must be set. for the tertiary functions of port 5, see chapter 18, ?port 5?.
ml610q407/ml610q408/ml610q409 user's manual chapter 12 synchronous serial port 12-8 12.2.8 serial port 0 mode register 1 (sio0mod1) address: 0f285h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 sio0mod1 ? ? s0neg s0ckt ? s0ck2 s0ck1 s0ck0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 sio0mod1 is a special function register (sfr) to set mode of the synchronous serial port 0. [description of bits] ? s0ck2 to s0ck0 (bits 2 to 0) the s0ck2 to s0ck0 bits are used to select the transfer clock of the synchronous serial port. when the internal clock is selected, this lsi is set to master mode and when the external clock is selected, it is set to slave mode. s0ck2 s0ck1 s0ck0 description 0 0 0 32 khz (initial value) 0 0 1 16khz 0 1 0 1/4 hsclk 0 1 1 1/8 hsclk 1 0 0 1/16 hsclk 1 0 1 1/32 hsclk 1 1 0 external clock 0 (p41/sck0) 1 1 1 external clock 0 (p45/sck0) ? s0ckt (bit 4) the s0ckt bit is used to select the phase of the transfer clock output. s0ckt description 0 clock type 0: output at the ?h? level by default (initial value). 1 clock type 1: output at the ?l? level by default. ? s0neg (bit 5) the s0neg bit is used to select the positive or negative logic of the transfer clock output. s0neg description 0 positive logic (initial value) 1 negative logic
ml610q407/ml610q408/ml610q409 user's manual chapter 12 synchronous serial port 12-9 12.2.9 serial port 1 mode register 1 (sio1mod1) address: 0f28dh access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 sio1mod1 ? ? s1neg s1ckt ? s1ck2 s1ck1 s1ck0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 sio1mod1 is a special function register (sfr) to set mode of the synchronous serial port 1. [description of bits] ? s1ck2 to s1ck0 (bits 2 to 0) the s1ck2 to s1ck0 bits are used to select the transfer clock of the synchronous serial port. when the internal clock is selected, this lsi is set to master mode and when the external clock is selected, it is set to slave mode. s1ck2 s1ck1 s1ck0 description 0 0 0 32 khz (initial value) 0 0 1 16khz 0 1 0 1/4 hsclk 0 1 1 1/8 hsclk 1 0 0 1/16 hsclk 1 0 1 1/32 hsclk 1 1 0 external clock 1 (p51/sck1) 1 1 1 external clock 1 (p55/sck1) ? s1ckt (bit 4) the s1ckt bit is used to select the phase of the transfer clock output. s1ckt description 0 clock type 0: output at the ?h? level by default (initial value). 1 clock type 1: output at the ?l? level by default. ? s1neg (bit 5) the s1neg bit is used to select the positive or negative logic of the transfer clock output. s1neg description 0 positive logic (initial value) 1 negative logic
ml610q407/ml610q408/ml610q409 user's manual chapter 12 synchronous serial port 12-10 12.3 description of operation 12.3.1 transmit operation when ?1? is written to the snmd1 bit and "0" is written to th e snmd0 bit of the serial port mode register (sionmod0), this lsi is set to the transmit mode. when transmitted data is written to the serial port transmit/receive buffer (sionb ufl, "h") and the snen bit of the serial port control register (sioncon) is set to ?1?, transm ission starts. when transmission of 8/16-bit data terminates, a synchronous serial port interrupt (sionint) occurs and the snen bit is set to ?0?. the transmitted data is output from the port 4's tertiary function (p42/sout0, p46/sout0) or from the port 5's tertiary function (p52/sout1, p56/sout1). when an internal clock is selected in the serial port mode register (sionmod1), the lsi is set to a master mode and when an external clock (sckn) is sel ected, the lsi is set to a slave mode. the serial port mode register (sionmod0) en ables selection of msb first/lsb first. the transmitted data output pin (soutn) and the transfer clock input/output pin (sck n) need to be set to the tertiary function for the port 4 or to the tertiary function for the port 5. the transmission operation waveforms of the synchronous serial port (8-bit length, lsb first) are shown in figures 12-2 to 12-5, for the clock type 0 (positive logic), clock type 0 (n egative logic), clock type 1 (positive logic), and clock type 1 (negative logic), respectively. figure 12-2 transmit operation waveforms of synchr onous serial port for clock type 0 (positive logic) (8-bit length, lsb first, n = 0, 1) figure 12-3 transmit operation waveforms of synchr onous serial port for clock type 0 (negative logic) (8-bit length, lsb first, n = 0, 1) figure 12-4 transmit operation waveforms of synchr onous serial port for clock type 1 (positive logic) (8-bit length, lsb first, n = 0, 1) snen 0 1 2 3 4 5 7 6 transmitted data sckn siontrh,l soutn sionint snen 0 1 2 3 4 5 7 6 transmitted data sckn siontrh,l soutn sionint snen 0 1 2 3 4 5 7 6 transmitted data sckn siontrh,l soutn sionint
ml610q407/ml610q408/ml610q409 user's manual chapter 12 synchronous serial port 12-11 figure 12-5 transmit operation waveforms of synchr onous serial port for clock type 1 (negative logic) (8-bit length, lsb first, n = 0, 1) snen 0 1 2 3 4 5 7 6 transmitted data sckn siontrh,l soutn sionint
ml610q407/ml610q408/ml610q409 user's manual chapter 12 synchronous serial port 12-12 12.3.2 receive operation when ?0? is written to the snmd1 bit and ?1? is written to th e snmd0 bit of the serial port mode register (sionmod0), this lsi is set to a receive mode. when the snen bit of the serial port control register (sioncon) is set to ?1?, reception starts. when reception of 8/16-bit data terminates, a synchronous serial port interrupt (sionint) occurs and the snen bit is set to ?0?. the received data is input from the tertia ry function pins (p40/sin0 or p44/sin0) or the tertia ry function pin (p50/sin1, p54sin ) of gpio. when an internal clock is selected in the serial port mode register (sionmod1), the lsi is set to a master mode and when an external clock (sckn) is sel ected, the lsi is set to a slave mode. the serial port mode register (sionmod0) en ables selection of msb first/lsb first. the received data input pin (sin n) and the transfer clock inpu t/output pin (sckn) need to be set to the tertiary function for the port 4 or to the secondary function for the port 5. the receive operation waveforms of the sy nchronous serial port (8-bit length, msb first) are shown in figures 12-6 to 12-9, for the clock type 0 (positive logic), clock type 0 (neg ative logic), clock type 1 (positive logic), and clock type 1 (negative logic), respectively. figure 12-6 receive operation waveforms of synchr onous serial port for clock type 0 (positive logic) (8-bit length, msb first) figure 12-7 receive operation waveforms of synchr onous serial port for clock type 0 (negative logic) (8-bit length, msb first) 0 snen 7 6 5 4 3 2 0 1 received data sckn sinn shift registe r sionint 7 6 5 4 3 2 1 sionrch,l 0 snen 7 6 5 4 3 2 0 1 received data sckn sinn shift registe r sionint 7 6 5 4 3 2 1 sionrch,l
ml610q407/ml610q408/ml610q409 user's manual chapter 12 synchronous serial port 12-13 figure 12-8 receive operation waveforms of synchr onous serial port for clock type 1 (positive logic) (8-bit length, msb first) figure 12-9 receive operation waveforms of synchr onous serial port for clock type 1 (negative logic) (8-bit length, msb first) note: when the sout0 pin is set to the tertiary function output in receive mode, a ?h? level is output from the sout0 pin. when the sout1 pin is set to the tertiary function output in receive mode, a ?h? level is output from the sout1 pin. 0 snen 7 6 5 4 3 2 0 1 received data sckn sinn shift registe r sionint 7 6 5 4 3 2 1 sionrch,l 0 snen 7 6 5 4 3 2 0 1 received data sckn sinn shift registe r sionint 7 6 5 4 3 2 1 sionrch,l
ml610q407/ml610q408/ml610q409 user's manual chapter 12 synchronous serial port 12-14 12.3.3 transmit/receive operation when ?1? is written to the snmd1 bit and "1" is written to th e snmd0 bit of the serial port mode register (sionmod0), this lsi is set to the transmit/receive mode. when the snen bit of the serial port control register (sioncon) is set to ?1?, transmission/reception starts. when transmission/reception of 8/16-bit data te rminates, a synchronous serial port inte rrupt (sionint) occurs and the snen bit is set to ?0?. the received data is input from the tertia ry function pins (p40/sin0 or p44/sin0) or the tertia ry function pin (p50/sin1, p54sin1) of gpio, and the transmitted data is output from the tertiary function pins (p42/sout0 or p46/sout0) or the tertiary function pin (p52/sout1) of gpio. when an internal clock is selected in the serial port mode register (sionmod1), the lsi is set to a master mode and when an external clock (sckn) is sel ected, the lsi is set to a slave mode. the serial port mode register (sionmod0) en ables selection of msb first/lsb first. the received data input pin (sinn), th e transmitted data output pin (soutn), a nd the transfer cloc k input/output pin (sckn) need to be set to the tertiary function for the port 4 or to the secondary function for the port 5. figure 12-10 shows the transmit/receive operation waveforms of the synchronous serial port (16-bit length, lsb first, clock types 0, positive logic). figure 12-10 transmit/receive operation waveforms of synchronous serial port (16-bit length, lsb first, clock type 0, positive logic)) 15 snen 0 1 2 3 12 13 15 14 received data sckn sinn shift registe r sionint 0 1 2 3 13 14 sionrch,l 15 soutn 0 1 2 3 12 13 14 transmitted data siontrh,l 12
ml610q407/ml610q408/ml610q409 user's manual chapter 12 synchronous serial port 12-15 12.4 specifying port registers to enable the ssio(ssio0, ssio1) function, the applicable bit of each related port re gister needs to be set. see chapter 17, "port 4" and chapter 18 "port 5" for detail about the port registers. 12.4.1 functioning p42 (sout0: output), p41 (sck 0: input/output), and p40 (sin0: input) as the ssio0/ ?master mode? set the p42md1 to p40md1 bits (p4mod1 register bits 2 to 0) to ?1? and the p42md0 to p40md0 bits (p4mod0 register bits 2 to 0) to ?0? for selecting the ssio as the tertiary function of the p42, p41 and p40. register name p4mod1 register (address: 0f225h) bit 7 6 5 4 3 2 1 0 bit name p47md1 p46md1 p45md1 p44md1 p43md1 p42md1 p41md1 p40md1 setting value * * * * * 1 1 1 register name p4mod0 register (address: 0f224h) bit 7 6 5 4 3 2 1 0 bit name p47md0 p46md0 p45md0 p44md0 p43md0 p42md0 p41md0 p40md0 setting value * * * * * 0 0 0 set p42c1-p41mc1 bits(bit2-bit1 of p4con1 register) to ?1 ?, set p42c0-p41c0 bits(bit2-bit1 of p4con0 register) to ?1?, and set p42dir-p41dir bits(bit2-bit1 of p4dir registe r) to ?0? for selecting the state mode of the p42 and p41 pins to cmos output. set the p40dir bit (p4dir register bit 0) to ?1? for selecting the p40 as an input pin. the set value ($) is arbitrary for the p40c1 and p40c0 bits. select an arbitrary state mode depending on the state of the external circuit to which the p40 pin is connected. register name p4con1 register (address: 0f223h) bit 7 6 5 4 3 2 1 0 bit name p47c1 p46c1 p45c1 p44c1 p43c1 p42c1 p41c1 p40c1 setting value * * * * * 1 1 $ register name p4con0 register (address: 0f222h) bit 7 6 5 4 3 2 1 0 bit name p47c0 p46c0 p45c0 p44c0 p43c0 p42c0 p41c0 p40c0 setting value * * * * * 1 1 $ register name p4dir regi ster (address: 0f221h) bit 7 6 5 4 3 2 1 0 bit name p47dir p46dir p45dir p44dir p43dir p42dir p41dir p40dir setting value * * * * * 0 0 1 the data of the p42d to p40d bits (p4d register bits 2 to 0) can either be "0" or "1". register name p4d register (address: 0f220h) bit 7 6 5 4 3 2 1 0 bit name p47d p46d p45d p44d p43d p42d p41d p40d setting value * * * * * ** ** ** * : bit not related to the ssio0 function ** : don?t care $: optional
ml610q407/ml610q408/ml610q409 user's manual chapter 12 synchronous serial port 12-16 12.4.2 functioning p42 (sout0: output), p41 (sck 0: input/output), and p40 (sin0: input) as the ssio0/ ?slave mode? set the p42md1 to p40md1 bits (p4mod1 register bits 2 to 0) to ?1? and the p42md0 to p40md0 bits (p4mod0 register bits 2 to 0) to ?0? for selecting the ssio as the tertiary function of the p42, p41 and p40. they are the same setting as those in the case of master mode. register name p4mod1 register (address: 0f225h) bit 7 6 5 4 3 2 1 0 bit name p47md1 p46md1 p45md1 p44md1 p43md1 p42md1 p41md1 p40md1 setting value * * * * * 1 1 1 register name p4mod0 register (address: 0f224h) bit 7 6 5 4 3 2 1 0 bit name p47md0 p46md0 p45md0 p44md0 p43md0 p42md0 p41md0 p40md0 setting value * * * * * 0 0 0 set the p42c1 bit (p4con1 register bit 2) to "1", the p42c0 bit (p4con0 register bit 2) to "1", and the p42dir bit (p4dir register bit 2) to "0" for selecting the p42 pin state mode to cmos output. set p41dir to p40dir bits (p4dir register bit 1 to 0) to ?1? for specifying the p41 and p40 as input pins. the set value ($) is arbitrary for the p41c1 to p40c1 bits and for the p41c0 to p40c0 bits. select an arbitrary input mode depending on the state of the external circuit to which the p41 or p40 pin is connected. register name p4con1 register (address: 0f223h) bit 7 6 5 4 3 2 1 0 bit name p47c1 p46c1 p45c1 p44c1 p43c1 p42c1 p41c1 p40c1 setting value * * * * * 1 $ $ register name p4con0 register (address: 0f222h) bit 7 6 5 4 3 2 1 0 bit name p47c0 p46c0 p45c0 p44c0 p43c0 p42c0 p41c0 p40c0 setting value * * * * * 1 $ $ register name p4dir regi ster (address: 0f221h) bit 7 6 5 4 3 2 1 0 bit name p47dir p46dir p45dir p44dir p43dir p42dir p41dir p40dir setting value * * * * * 0 1 1 the data of the p42d to p40d bits (p4d register bits 2 to 0) can either be "0" or "1". register name p4d register (address: 0f220h) bit 7 6 5 4 3 2 1 0 bit name p47d p46d p45d p44d p43d p42d p41d p40d setting value * * * * * ** ** ** * : bit not related to the ssio0 function ** : don?t care $: optional
ml610q407/ml610q408/ml610q409 user's manual chapter 12 synchronous serial port 12-17 12.4.3 functioning p46 (sout0: output), p45 (s ck0: input/output) and p44 (sin0: input) as the ssio0/ ?master mode? set p46md1-p44md1 bits(bit6-bit4 of p4mod1 register) to ?1? and set p46md0-p44md0(bit6-bit4 of p4mod0 register) to ?0?, for specifying the ssio0 as the tertialy function of p46, p45 and p44. set p40md1 bit(bit0 of p4mod1) to ?0?, and set p40 to be primaly or secondary function as not to be ssio function. register name p4mod1 register (address: 0f225h) bit 7 6 5 4 3 2 1 0 bit name p47md1 p46md1 p45md1 p44md1 p43md1 p42md1 p41md1 p40md1 setting value * 1 1 1 * * * 0 register name p4mod0 register (address: 0f224h) bit 7 6 5 4 3 2 1 0 bit name p47md0 p46md0 p45md0 p44md0 p43md0 p42md0 p41md0 p40md0 setting value * 0 0 0 * * * * set p46c1-p45mc1 bits(bit6-bit5 of p4con1 register) to ?1 ?, set p46c0-p45c0 bits(bit6-bit5 of p4con0 register) to ?1?, and set p46dir-p45dir bits(bit6-bit5 of p4dir registe r) to ?0? for selecting the state mode of the p46 and p45 pins to cmos output. set p44dir bit(bit4 of p4dir register) to ?1? for specifying the p44 as an input pin. the set value ($) is arbitrary for the p44c1 and p44c0 bits. select an arbitrary state mode depending on the state of the external circuit to which the p44 pin is connected. register name p4con1 register (address: 0f223h) bit 7 6 5 4 3 2 1 0 bit name p47c1 p46c1 p45c1 p44c1 p43c1 p42c1 p41c1 p40c1 setting value * 1 1 $ * * * * register name p4con0 register (address: 0f222h) bit 7 6 5 4 3 2 1 0 bit name p47c0 p46c0 p45c0 p44c0 p43c0 p42c0 p41c0 p40c0 setting value * 1 1 $ * * * * register name p4dir regi ster (address: 0f221h) bit 7 6 5 4 3 2 1 0 bit name p47dir p46dir p45dir p44dir p43dir p42dir p41dir p40dir setting value * 0 0 1 * * * * the p46d to p44d bits (p4d register bits 6 to 4) da ta can either be "0" or "1 " (not need to be set). register name p4d register (address: 0f220h) bit 7 6 5 4 3 2 1 0 bit name p47d p46d p45d p44d p43d p42d p41d p40d setting value * ** ** ** * * * * * : bit not related to the ssio0 function ** : don?t care $: optional
ml610q407/ml610q408/ml610q409 user's manual chapter 12 synchronous serial port 12-18 12.4.4 functioning p46 (sout0: output), p45 (s ck0: input/output) and p44 (sin0: input) as the ssio0/ ?slave mode? set p46md1-p44md1 bits(bit6-bit4 of p4mod1 register) to ?1? and set p46md0-p44md0(bit6-bit4 of p4mod0 register) to ?0?, for specifying the ssio0 as the tertialy function of p46, p45 and p44. set p40md1 bit(bit0 of p4mod1) to ?0?, and set p40 to be primaly or secondary f unction as not to be ssio functi on. they are the same setting as those in the case of master mode. register name p4mod1 register (address: 0f225h) bit 7 6 5 4 3 2 1 0 bit name p47md1 p46md1 p45md1 p44md1 p43md1 p42md1 p41md1 p40md1 setting value * 1 1 1 * * * 0 register name p4mod0 register (address: 0f224h) bit 7 6 5 4 3 2 1 0 bit name p47md0 p46md0 p45md0 p44md0 p43md0 p42md0 p41md0 p40md0 setting value * 0 0 0 * * * * set p46c1 bit(bit6 of p4con1 register) to ?1?, set p46c0 bit( bit6 of p4con0 register) to ?1?, and set p46dir bit(bit6 of p4dir register) to ?0? for selecting the p46 pin state mode to cmos output. set p45dir-p44dir bits(bit5-4 of p4dir register) to ?1? for specifying the p45 and p44 as input pins. the set value ($) is arbitrary for the p45c1 to p44c1 bits and for the p45c0 to p44c0 bits. select an arbitrary input mode depending on the state of the external circuit to which the p45 or p44 pin is connected. register name p4con1 register (address: 0f223h) bit 7 6 5 4 3 2 1 0 bit name p47c1 p46c1 p45c1 p44c1 p43c1 p42c1 p41c1 p40c1 setting value * 1 $ $ * * * * register name p4con0 register (address: 0f222h) bit 7 6 5 4 3 2 1 0 bit name p47c0 p46c0 p45c0 p44c0 p43c0 p42c0 p41c0 p40c0 setting value * 1 $ $ * * * * register name p4dir regi ster (address: 0f221h) bit 7 6 5 4 3 2 1 0 bit name p47dir p46dir p45dir p44dir p43dir p42dir p41dir p40dir setting value * 0 1 1 * * * * the p46d to p44d bits (p4d register bits 6 to 4) da ta can either be "0" or "1 " (not need to be set). register name p4d register (address: 0f220h) bit 7 6 5 4 3 2 1 0 bit name p47d p46d p45d p44d p43d p42d p41d p40d setting value * ** ** ** * * * * * : bit not related to the ssio0 function ** : don?t care $: optional
ml610q407/ml610q408/ml610q409 user's manual chapter 12 synchronous serial port 12-19 12.4.5 functioning p52 (sout1: output), p51 (sck 1: input/output), and p50 (sin1: input) as the ssio1/ ?master mode? set the p52md1 to p50md1 bits (p5mod1 register bits 2 to 0) to "1", and set the p52md0 to p50md0 bits (p5mod0 register bits 2 to 0) to "0" for specifying the ssio1 as the secondary function of the p52, p51, and p50. register name p5mod1 regi ster (address: 0f22dh) bit 7 6 5 4 3 2 1 0 bit name ? p56md1 p55md1 p54md1 ? p52md1 p51md1 p50md1 setting value * * * * * 1 1 1 register name p5mod0 regi ster (address: 0f22ch) bit 7 6 5 4 3 2 1 0 bit name ? p56md0 p55md0 p54md0 ? p52md0 p51md0 p50md0 setting value * * * * * 0 0 0 set the p52c0 to p51c0 bits (p5con0 register bits 2 to 1) to "1", and the p52dir to p51dir bits (p5dir register bits 2 to 1) to "0" for selecting the p52 and p51 pin state mode to cmos output. set the p50dir bit (p5dir register bit 0) to ?1? for selecting the p50 as an input pin. the set value ($) is arbitrary for the p5ud and p50c0 bits. se lect an arbitrary state mode depending on the state of the external circuit to which the p50 pin is connected. register name p5con1 regi ster (address: 0f22bh) bit 7 6 5 4 3 2 1 0 bit name ? ? ? ? ? ? ? p5ud setting value * * * * * * * $ register name p5con0 regi ster (address: 0f22ah) bit 7 6 5 4 3 2 1 0 bit name p57c0 p56c0 p55c0 p54c0 p53c0 p52c0 p51c0 p50c0 setting value * * * * * 1 1 $ register name p5dir regi ster (address: 0f229h) bit 7 6 5 4 3 2 1 0 bit name p57dir p56dir p55dir p54dir p53dir p52dir p51dir p50dir setting value * * * * * 0 0 1 the p52d to p50d bits (p5d register bits 2 to 0) da ta can either be "0" or "1 " (not need to be set). register name p5d register (address: 0f228h) bit 7 6 5 4 3 2 1 0 bit name p57d p56d p55d p54d p53d p52d p51d p50d setting value * * * * * ** ** ** * : bit not related to the ssio1 function ** : don?t care $: optional
ml610q407/ml610q408/ml610q409 user's manual chapter 12 synchronous serial port 12-20 12.4.6 functioning p52 (sout1: output), p51 (sck 1: input/output), and p50 (sin1: input) as the ssio1/ ?slave mode? set the p52md1 to p50md1 bits (p5mod1 register bits 2 to 0) to "1", and set the p52md0 to p50md0 bits (p5mod0 register bits 2 to 0) to "0" for specifying the ssio as the tertialy function of the p52, p51, and p50. they are the same setting as those in the case of master mode. register name p5mod1 regi ster (address: 0f22dh) bit 7 6 5 4 3 2 1 0 bit name ? p56md1 p55md1 p54md1 ? p52md1 p51md1 p50md1 setting value * * * * * 1 1 1 register name p5mod0 regi ster (address: 0f22ch) bit 7 6 5 4 3 2 1 0 bit name ? p56md0 p55md0 p54md0 ? p52md0 p51md0 p50md0 setting value * * * * * 0 0 0 set the p52c0 bit (p5con0 register bit 2) to "1", and the p52dir bit (p5dir register bit 2) to "0" for selecting the p52 pin state mode to cmos output. set p51dir to p50dir bits (p5dir register bits 1 to 0) to ?1? for selecting the p51 and p50 as input pins. the set value ($) is arbitrary for the p5ud bits and for the p51c0 to p50c0 bits. select an arbitrary input mode depending on the state of the external circuit to which the p51 or p50 pin is connected. register name p5con1 regi ster (address: 0f22bh) bit 7 6 5 4 3 2 1 0 bit name ? ? ? ? ? ? ? p5ud setting value * * * * * * * $ register name p5con0 regi ster (address: 0f22ah) bit 7 6 5 4 3 2 1 0 bit name p57c0 p56c0 p55c0 p54c0 p53c0 p52c0 p51c0 p50c0 setting value * * * * * 1 $ $ register name p5dir regi ster (address: 0f229h) bit 7 6 5 4 3 2 1 0 bit name p57dir p56dir p55dir p54dir p53dir p52dir p51dir p50dir setting value * * * * * 0 1 1 the p52d to p50d bits (p5d register bits 2 to 0) da ta can either be "0" or "1 " (not need to be set). register name p5d register (address: 0f228h) bit 7 6 5 4 3 2 1 0 bit name p57d p56d p55d p54d p53d p52d p51d p50d setting value * * * * * ** ** ** * : bit not related to the ssio1 function ** : don?t care $: optional
ml610q407/ml610q408/ml610q409 user's manual chapter 12 synchronous serial port 12-21 12.4.7 functioning p56 (sout1: output), p55 (sck 1: input/output), and p54 (sin1: input) as the ssio1/ ?master mode? set the p56md1 to p54md1 bits (p5mod1 register bits 6 to 4) to "1", and set the p56md0 to p54md0 bits (p5mod0 register bits 6 to 4) to "0" for specifying the ssio1 as the secondary function of the p56, p55, and p54. register name p5mod1 regi ster (address: 0f22dh) bit 7 6 5 4 3 2 1 0 bit name ? p56md1 p55md1 p54md1 ? p52md1 p51md1 p50md1 setting value * 1 1 1 * * * * register name p5mod0 regi ster (address: 0f22ch) bit 7 6 5 4 3 2 1 0 bit name ? p56md0 p55md0 p54md0 ? p52md0 p51md0 p50md0 setting value * 0 0 0 * * * * set the p56c0 to p55c0 bits (p5con0 register bits 6 to 5) to "1", and the p56dir to p55dir bits (p5dir register bits 6 to 5) to "0" for selecting the p56 and p55 pin state mode to cmos output. set the p54dir bit (p5dir register bit 4) to ?1? for selecting the p54 as an input pin. the set value ($) is arbitrary for the p5ud and p54c0 bits. se lect an arbitrary state mode depending on the state of the external circuit to which the p54 pin is connected. register name p5con1 regi ster (address: 0f22bh) bit 7 6 5 4 3 2 1 0 bit name ? ? ? ? ? ? ? p5ud setting value * * * * * * * $ register name p5con0 regi ster (address: 0f22ah) bit 7 6 5 4 3 2 1 0 bit name p57c0 p56c0 p55c0 p54c0 p53c0 p52c0 p51c0 p50c0 setting value * 1 1 $ * * * * register name p5dir regi ster (address: 0f229h) bit 7 6 5 4 3 2 1 0 bit name p57dir p56dir p55dir p54dir p53dir p52dir p51dir p50dir setting value * 0 0 1 * * * * the p56d to p54d bits (p5d register bits 6 to 4) da ta can either be "0" or "1 " (not need to be set). register name p5d register (address: 0f228h) bit 7 6 5 4 3 2 1 0 bit name p57d p56d p55d p54d p53d p52d p51d p50d setting value * ** ** ** * * * * * : bit not related to the ssio1 function ** : don?t care $: optional
ml610q407/ml610q408/ml610q409 user's manual chapter 12 synchronous serial port 12-22 12.4.8 functioning p56 (sout1: output), p55 (s ck1: input/output), and p54 (sin1: input) as the ssio1/ ?slave mode? set the p56md1 to p54md1 bits (p5mod1 register bits 6 to 4) to "1", and set the p56md0 to p54md0 bits (p5mod0 register bits 6 to 4) to "0" for specifying the ssio as the tertialy function of the p52, p51, and p50. they are the same setting as those in the case of master mode. register name p5mod1 regi ster (address: 0f22dh) bit 7 6 5 4 3 2 1 0 bit name ? p56md1 p55md1 p54md1 ? p52md1 p51md1 p50md1 setting value * 1 1 1 * * * 1 register name p5mod0 regi ster (address: 0f22ch) bit 7 6 5 4 3 2 1 0 bit name ? p56md0 p55md0 p54md0 ? p52md0 p51md0 p50md0 setting value * 0 0 0 * * * * set the p56c0 bit (p5con0 register bit 6) to "1", and the p56dir bit (p5dir register bit 6) to "0" for selecting the p56 pin state mode to cmos output. set p55dir to p54dir bits (p5dir register bits 5 to 4) to ?1? for selecting the p55 and p54 as input pins. the set value ($) is arbitrary for the p5ud bits and for the p55c0 to p54c0 bits. select an arbitrary input mode depending on the state of the external circuit to which the p55 or p54 pin is connected. register name p5con1 regi ster (address: 0f22bh) bit 7 6 5 4 3 2 1 0 bit name ? ? ? ? ? ? ? p5ud setting value * * * * * * * $ register name p5con0 regi ster (address: 0f22ah) bit 7 6 5 4 3 2 1 0 bit name p57c0 p56c0 p55c0 p54c0 p53c0 p52c0 p51c0 p50c0 setting value * 1 $ $ * * * * register name p5dir regi ster (address: 0f229h) bit 7 6 5 4 3 2 1 0 bit name p57dir p56dir p55dir p54dir p53dir p52dir p51dir p50dir setting value * 0 1 1 * * * * the p56d to p54d bits (p5d register bits 6 to 4) da ta can either be "0" or "1 " (not need to be set). register name p5d register (address: 0f228h) bit 7 6 5 4 3 2 1 0 bit name p57d p56d p55d p54d p53d p52d p51d p50d setting value * ** ** ** * * * * * : bit not related to the ssio1 function ** : don?t care $: optional
chapter 13 uart
ml610q407/ml610q408/ml610q409 user's manual chapter 13 uart 13-1 13. uart 13.1 overview this lsi includes 1 channel of uart (u niversal asynchronous receiver transmitte r) which is an asynchronous serial interface. for the input clock, see chapter 6, ?clock generation circuit?. the use of uart requires setting of the secondary functions of port 4. for the secondary functions of port 4, see chapter 17, ?port 4?. 13.1.1 features ? 5-bit/6-bit/7-bit/8-bit data length selectable. ? odd parity, even parity, or no parity selectable. ? 1 stop bit or 2 stop bits selectable. ? provided with parity error flag , overrun error flag, framing error flag , and transmit buffer status flag. ? positive logic or negative logic selectable as communication logic. ? lsb first or msb first selectab le as a communication direction. ? communication speed: settable within the range of 200bps to 38400bps. ? built-in baud rate generator. 13.1.2 configuration figure 13-1 shows the conf iguration of the uart. ua0buf : uart0 transmit/receive buffer ua0brth,l : uart0 baud rate h and l are: ua0con : uart0 control register ua0mod0,1 : uart0 mode registers 0 and 1 ua0stat : uart0 status register figure 13-1 configuration of uart p42/rxd0 ua0buf shift register ua0int band rate generator ua0con ua0mod0,1 ua0stat uart controller p43/txd0 lsclk hsclk data bus ua0brth,l lsclk 2 p02/rxd0
ml610q407/ml610q408/ml610q409 user's manual chapter 13 uart 13-2 13.1.3 list of pins pin name i/o function p02/rxd0 i uart0 data input pin used for the primary func tion of the p02 pin. p42/rxd0 i uart0 data input pin used for the secondary func tion of the p42 pin. p43/txd0 o uart0 data output pin used for the secondary func tion of the p43 pin. 13.2 description of registers 13.2.1 list of registers address name symbol (byte) symbol (word) r/w size initial value 0f290h uart0 transmit/receive buffer ua0buf r/w 8 00h 0f291h uart0 control register ua0con r/w 8 00h 0f292h uart0 mode register 0 ua0mod0 r/w 8/16 00h 0f293h uart0 mode register 1 ua0mod1 ua0mod r/w 8 00h 0f294h uart0 baud rate register l ua0brtl r/w 8/16 0ffh 0f295h uart0 baud rate register h ua0brth ua0brt r/w 8 0fh 0f296h uart0 status register ua0stat r/w 8 00h
ml610q407/ml610q408/ml610q409 user's manual chapter 13 uart 13-3 13.2.2 uart0 transmit/receive buffer (ua0buf) address: 0f290h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 ua0buf u0b7 u0b6 u0b5 u0b4 u0b3 u0b2 u0b1 u0b0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 ua0buf is a special function regi ster (sfr) to store the transm itted/received data of the uart. in transmit mode, write transmission data to ua0buf. to tr ansmit the data consecutively, confirm the u0ful flag of the uart0 status register (ua0stat) becomes "0", then write the next transmitted data to the ua0buf. any value written to ua0buf can be read. in receive mode, since data received at termination of reception is stored in ua0buf, read the contents of uabuf using the uart0 interrupt at termin ation of reception. at continuous r eception, ba0buf is updated whenever reception terminates. any write to ba0b uf is disabled in receive mode. the bits, which are not required when any of the 5- to 8-bit data length is selected, become invalid in transmit mode and are set to ?0? in receive mode. note: for operation in transmit mode, be sure to set the transmit mode (ua0mod0 and ua0mod1) before setting the transmitted data in uaobuf.
ml610q407/ml610q408/ml610q409 user's manual chapter 13 uart 13-4 13.2.3 uart0 control register (ua0con) address: 0f291h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 ua0con D D D D D D D u0en r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 ua0con is a special function register (sfr) to start/stop communication of the uart. [description of bits] ? u0en (bit 0) the u0en bit is used to specify the uart communication operation start. when u0en is set to ?1?, uart communication starts. in transmit mode, this bit is automatically set to ?0? at termination of transmission. in receive mode, receive operation is c ontinued. to terminate reception, set the bit to ?0? by software. u0en description 0 stops communication. (initial value) 1 starts communication
ml610q407/ml610q408/ml610q409 user's manual chapter 13 uart 13-5 13.2.4 uart0 mode register 0 (ua0mod0) address: 0f292h access: r/w access size: 8/16 bit initial value: 00h 7 6 5 4 3 2 1 0 ua0mod0 u0rss u0rsel u0ck1 u0ck0 u0io r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 ua0mod0 is a special function register (sfr) to set the transfer mode of the uart. [description of bits] ? u0io (bit 0) the u0io bit is used to sel ect transmit or receive mode. u0io description 0 transmit mode (initial value) 1 receive mode ? u0ck1, u0ck0 (bits 2, 1) the u0ck1 and u0ck0 bits are used to select the clock to be input to the baud rate generator of the uart0. u0ck1 u0ck0 description 0 0 lsclk (initial value) 0 1 lsclk 2 1 hsclk ? u0rsel (bit 4) the u0rsel bit is used to select the received data input pin for the uart0. u0rsel description 0 selects the p02 pin. (initial value) 1 selects the p42 pin. ? u0rss (bit 5) u0rss is the bit that selects the uart0 received data input sampling timing. u0rss description 0 value set in the ua0brth and ua0b rtl registers/2 (initial value) 1 value set in the ua0brt h and ua0brtl registers/2-1 note: ?always set the ua0mod0 register while communication is stopped, and do not rewrite it during communication. ?when specifying lsclk x 2 for the clock, enable the operation of the low-speed double clock by setting bit 2 (enmlt) of the frequency control register 1 (fcon1) to ?1?. ?when selecting the p42 pin as the recei ved data input pin, it is necessary to configure settings for the port 4 secondary functions. for the secondary functi ons of port 4, see chapter 17, ?port 4?.
ml610q407/ml610q408/ml610q409 user's manual chapter 13 uart 13-6 13.2.5 uart0 mode register 1 (ua0mod1) address: 0f293h access: r/w access size: 8/16 bit initial value: 00h 7 6 5 4 3 2 1 0 ua0mod1 u0dir u0neg u0stp u0pt1 u0pt0 u0lg1 u0lg0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 ua0mod1 is a special function register (sfr) to set the transfer mode of the uart. [description of bits] ? u0lg1, u0lg0 (bits 1, 0) the u0lg1 and u0lg0 bits are used to specify the data length in the communication of the uart. u0lg1 u0lg0 description 0 0 8-bit length (initial value) 0 1 7-bit length 1 0 6-bit length 1 1 5-bit length ? u0pt1, u0pt0 (bits 3, 2) the u0pt1 and u0pt0 bits are used to select ?even parity?, odd parity?, or ?no parity? in the communication of the uart. u0pt1 u0pt0 description 0 0 even parity (initial value) 0 1 odd parity 1 * no parity bit ? u0stp (bit 4) the u0stp bit is used to select the stop bit length in the communication of the uart. u0stp description 0 1 stop bit (initial value) 1 2 stop bits
ml610q407/ml610q408/ml610q409 user's manual chapter 13 uart 13-7 ? u0neg (bit 5) the u0neg bit is used to select positive logic or negative logic in the communication of the uart. u0neg description 0 positive logic (initial value) 1 negative logic ? u0dir (bit 6) the u0dir bit is used to select lsb first or msb first in the communication of the uart. u0dir description 0 lsb first (initial value) 1 msb first note: always set the ua0mod1 register while communication is stopped, and do not rewrite it during communication.
ml610q407/ml610q408/ml610q409 user's manual chapter 13 uart 13-8 13.2.6 uart0 baud rate registers l, h (ua0brtl, ua0brth) address: 0f294h access: r/w access size: 8/16 bit initial value: 0ffh 7 6 5 4 3 2 1 0 ua0brtl u0br7 u0br6 u0br5 u0br4 u0br3 u0br2 u0br1 u0br0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 1 1 1 1 1 1 1 1 address: 0f295h access: r/w access size: 8-bit initial value: 0fh 7 6 5 4 3 2 1 0 ua0brth D D D D u0br11 u0br10 u0br9 u0br8 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 1 1 1 1 ua0brtl and ua0brth are special function registers (sfrs) to set the count value of the baud rate generator which generates baud rate clocks. for the relationship between the count value of the baud rate generator and baud rate, see section 13.3.2, ?baud rate?. note: always set the ua0brtl and ua0brth registers while communication is stopped, and do not rewrite them during communication.
ml610q407/ml610q408/ml610q409 user's manual chapter 13 uart 13-9 13.2.7 uart0 status register (ua0stat) address: 0f296h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 ua0stat u0ful u0per u0oer u0fer r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 ua0stat is a special function register (sfr) to indicate the state of tran smit or receive operation of the uart. when any data is written to ua0stat, all the flags are initialized to ?0?. [description of bits] ? u0fer (bit 0) the u0fer bit is used to indicate occu rrence of a framing error of the uart. when an error occurs in the start or stop bit, the u0fer bit is set to ?1 ?. this bit is updated each time reception is completed. the u0fer bit is fixed to ?0? in transmit mode. u0fer description 0 no framing error (initial value) 1 with framing error ? u0oer (bit 1) the u0oer bit is used to indicate occu rrence of an overrun error of the uart. if the received data in the transmit/receive buffer (ua0buf) is received again befo re it is read, this bit is set to ?1?. even if reception is stopped by the u0en bit and then reception is restarte d, this bit is set to ?1? unless the previously received data is not read. therefore, make sure that data is always read from the transmit/receive buffer even if the data is not required. the u0oer bit is fixed to ?0? in transmit mode. u0oer description 0 no overrun error (initial value) 1 overrun error ? u0per (bit 2) the u0per bit is used to indicate occu rrence of a parity error of the uart. when the parity of the received data and the parity bit attached to the data do not coincide, this bit is set to ?1?. u0per is updated whenever data is received. the u0per bit is fixed to ?0? in transmit mode. u0per description 0 no parity error (initial value) 1 parity error
ml610q407/ml610q408/ml610q409 user's manual chapter 13 uart 13-10 ? u0ful (bit 3) the u0ful bit is used to indicate the stat e of the transmit/receive buffer of the uart. when the transmitted data is written in ua0buf in transmit mode, this bit is set to ?1? and when this transmitted data is transferred to the shift register, this bit is set to ?0?. to transmit the data consecutively, confirm the u0ful flag becomes "0", then write the next transmitted data to the ua0buf. the u0ful bit is fixed to ?0? in receive mode. u0ful description 0 there is no data in the transmit/r eceive buffer. (initial value) 1 there is data in the transmit/receive buffer.
ml610q407/ml610q408/ml610q409 user's manual chapter 13 uart 13-11 13.3 description of operation 13.3.1 transfer data format in the transfer data format, one frame contains a start bit, a data bit, a parity bit, and a stop bit. in this format, 5 to 8 b its can be selected as data bit. for the parity bit, ?with parity bit?, ?without parity bit?, ?even parity?, or ?odd parity? can be selected. for the stop bit, ?1 stop bit? or ?2 stop bits? are available and for the tr ansfer direction, ?l sb first? or ?msb first? are available for selection. for serial input/output logic, positive logic or negative logic can be selected. all these options are set with the uart0 mode register (ua0mod1). figure 13-2 and figure 13-3 show the pos itive logic input/output fo rmat and negative logi c input/output format, respectively. figure 13-2 positive logic input/output format figure 13-3 negative logic input/output format start bit 1 2 3 4 5 6 7 8 parity bit data bit 1 frame ?1 frame max. ... 12 bits min. ... 7 bits ?data bit length ... 8 to 5 bits variable ?parity bit ... with or without parity bit selectable odd or even parity selectable ?stop bit ... 1 or 2 stop bits selectable stop bit stop bit start bit 1 2 3 4 5678 parity bit data bit 1 frame stop bit stop bit ?1 frame max. ... 12 bits min. ... 7 bits ?data bit length ... 8 to 5 bits variable ?parity bit ... with or without parity bit selectable odd or even parity selectable ?stop bit ... 1 or 2 stop bits selectable
ml610q407/ml610q408/ml610q409 user's manual chapter 13 uart 13-12 13.3.2 baud rate baud rates are generated by the baud generator. the baud rate generator generates a baud rate by counting the clock selected by the baud rate clock selection bits (u0ck1, u0ck0) of the uart0 mode register 0 (ua0mod0). the count value of the baud rate generator can be set by writing it in the uart0 baud rate register h or l (ua0brth, ua0brtl). the maximum count is 4096. the setting values of ua0brth and ua0brtl are expressed by the following equation. clock frequency (hz) ua0brth, l baud rate (bps) ? table 13-2 lists the count values for typical baud rates. table 13-2 count values for typical baud rates baud rate generator clock selection baud rate generator counter value baud rate baud rate clock u0ck1 u0ck0 count value period of one bit ua0brth ua0brtl error [%] 1200bps 32.768khz 0 0 27 approx imately 824us 00h 1ah 1.1 32.768khz 0 0 14 approximately 427us 00h 0dh -2.5 2400bps 65.536khz 0 1 27 approxim ately 412us 00h 1ah 1.1 32.768khz 0 0 7 approximately 214us 00h 06h -2.5 65.536khz 0 1 14 approximately 214us 00h 0dh -2.5 500khz 104 approximat ely 208us 00h 67h 0.2 4800bps 2mhz 1 417 approximately 208.5us 01h a0h -0.1 65.536khz 0 1 7 approximately 107us 00h 06h -2.5 500khz 52 approximately 104us 00h 33h 0.2 9600bps 2mhz 1 208 approximately 104us 00h cfh 0.2 19200bps 2mhz 1 104 approximately 52us 00h 67h 0.2 38400bps 2mhz 1 52 approximately 26us 00h 33h 0.2 note: when using 65.536khz (lsclk x 2) for the baud rate genera tor input clock, enable the operation of the low-speed double clock by setting bit 2 (enm lt) of the frequency control re gister 1 (fcon1) to ?1?. when the baud rate clock generator input clock selecti on is set to 500khz or 2mhz, an error of 500khz25% or 2mhz25% may occur. to set the baud ra te with accuracy, set the baud rate ge nerator counter valu e by referring to the frequency measurement modes for timers 2 and 3 (sections 9.3.3). internal logic voltage (v ddl ) is changed by oscm2 bit. v ddl becomes typ.1.2v when oscm2 is set to ?0? and 500khz oscillation is selected. v ddl becomes typ.1.5v when oscm2 is set to ?1? and 2mhz oscillation is selected. . ensure to write this bit when the high-speed clock oscillator circuit stops oscillating (during fcon1 register's enosc bit is "0").
ml610q407/ml610q408/ml610q409 user's manual chapter 13 uart 13-13 13.3.3 transmitted data direction figure 13-4 shows the relationship between the tran smit/receive buffer and the transmitted/received data. figure 13-4 relationship between transmit/rec eive buffer and transmitted/received data note: when the txd0 pin is set to serve the secondary function output in receive mode, "h" le vel is output from the txd0 output. u0b6 u0b3 u0b7 u0b5 u0b2 u0b1 u0b4 u0b0 lsb reception lsb rece p tion data len g th: 8 bits data length: 7 bits data len g th: 6 bits u0b7 is ? 0 ? at com p letion of data length: 5 bits msb reception msb rece p tion u0b6 u0b3 u0b5 u0b2 u0b1 u0b4 u0b0 lsb reception lsb reception msb reception msb reception u0b7 and u0b6 are ? 0 ? at com p letion u0b3 u0b5 u0b2 u0b1 u0b4 u0b0 lsb reception lsb reception msb reception msb reception u0b7, u0b6, and u0b5 are ? 0 ? at completion of reception. u0b3 u0b2 u0b1 u0b4 u0b0 lsb reception lsb reception msb reception msb reception
ml610q407/ml610q408/ml610q409 user's manual chapter 13 uart 13-14 13.3.4 transmit operation transmission is started by setting the u0io bit of the uart0 mode register 0 (ua0mod0) to ?0? to select transmit mode and setting the u0en bit of the uart0 control register (ua0con) to ?1?. figure 13-5 shows the operation timing for transmission. when the u0en bit is set to ?1? ( c ), the baud rate generator generates an intern al transfer clock of the baud rate set and starts transmission. the start bit is output to the txd0 pin by the falling edge of the internal transfer clock ( d ). subsequently, the transmitted data, a parity bit, and a stop bit are output. when the start bit is output ( d ), a uart0 interrupt is requested. in the uart0 interrupt routine, the next data to be transmitted is written to the tr ansmit/receive buffer (ua0buf). when the next data to be transmitted is written to the transmit/receive buffer (ua0 obuf), the transmit buffer status flag (u0ful) is set to ?1? ( e ) and a uart0 interrupt is requested on the falling edge of the internal transfer clock ( f ) after transmission of the stop bit. if the uar t0 interrupt routine is terminated without writing the next data to the transmit/receive buffer, the u0fu l bit is not set to ?1? ( g ) and transmission continues up to the transmission of the stop bit, then the u0en bit is reset to ?0? and a uart0 interrupt is requested. the valid period for the next transmit data to be written to the transmit/receive buffer is from the generation of an interrupt to the termination of stop bit transmission. ( h )
ml610q407/ml610q408/ml610q409 user's manual chapter 13 uart 13-15 figure 13-5 operation timing in transmission 1 f g h h system clock ua0buf write instruction u0en set instruction 1st data 2nd data brt brt start 0 1 2 7 parit y start 0 2 7 parit y stop c d transmit/receive buffer write enable period transmit/receive buffer write enable period sysclk ua0buf u0en set signal internal transfer clock txd0 output ua0int u0ful u0en sto p e
ml610q407/ml610q408/ml610q409 user's manual chapter 13 uart 13-16 13.3.5 receive operation select the received data pin using the u0rsel bit of th e uart0uart0 mode register 0 (ua0mod0). select the receive mode by setting the u0io bit of the uart0 mode register 0 (ua0mod0) to "1". then, set th e u0en bit of the uart0 control register (ua0con) to "1" to start receiving data. figure 13-6 shows the operation timing for reception. when receive operation starts, the lsi checks the data sent to the input pin rxd0 and waits fo r the arrival of a start bit. when detecting a start bit ( c ), the lsi generates the internal transfer clock of the baud rate set with the start bit detect point as a reference and performs receive operation. the shift register shifts in the data input to rxd on the rising edge of the internal transfer clock. the data and parity bit are shifted into the shift regi ster and 5- to 8- bit received data is tran sferred to the transmit/r eceive buffer (ua0buf) concurrently with the fall of the internal transfer clock of e . the lsi requests a uart0 interrupt on the rising edge of the internal transfer clock subsequent to the internal transfer clock by which the recei ved data was fetched ( f ) and checks for a stop bit error and a pa rity bit error. when an error is detected, the lsi sets the corresponding bit of the uart0 status register (ua0stat) to ?1?. parity error : s0per 1 overrun error : s0oer 1 framing error : s0fer 1 as shown in figure 13-6, the rise of the internal transfer clock is set so that it may fall into the middle of the bit interval of the received data. reception continues until the u0en bit is reset to ?0? by the program. when the u0en bit is reset to ?0? during reception, the received data may be destro yed. when the u0en bit is reset to ?0 ? during the ?u0en reset enable period? in figure 13-6, the received data is protected.
ml610q407/ml610q408/ml610q409 user's manual chapter 13 uart 13-17 figure 13-6 operation timing in reception brt brt 1 2 7 parit y sto p start 0 1 6 7 start 0 1 6 7 parit y stop sto p start 1 2 7 1st data 2nd data : parity error : overrun error f detection of start bit g e d c parity error, overrun error, framing error detected request for uart0 interrupt stop receiving because the start bit is not loaded u0en rxd internal transfer shift register (input stage) ua0int u0per u0oer transmit/receive buffe r u0en reset enable period start parity 0 stop parity 0
ml610q407/ml610q408/ml610q409 user's manual chapter 13 uart 13-18 13.3.5.1 detection of start bit the start bit is sampled using the baud rate generator cloc k (lsclk, lsclk x 2, hsclk) selected by the u0ck1 and u0ck0 bits of the uartn mode register 0 (ua0mod0). therefore, the start bit detection may be delayed for one cycle of the baud rate generate clock at the maximum. figure 13-7 shows the start bit detection timing. figure 13-7 start bit detection timing (positive logic) 13.3.5.2 sampling timing when the start bit is detected , the received data that was input to the rxd0 is sampled almost at the center of the baud rate, then loaded to the shift register. the loading sampling timing of this shift register can be adju sted for one clock of the baud rate generator clock, using the u0rss bit of the uart0 mode register 0 (ua0mod0). figure 13-8 shows the relationship between the u0rss bit and the sampling timing. (1) when the baud rate generator count value is "7" (odd) (2) when the baud rate generator count value is "8" (even) figure 13-8 relationship between uorss bit and sampling timing baud rate generator clock rxd0 0 3 2 7 0 3 2 7 sampling timing u0rss=1 u0rss=0 count value = 8 baud rate generator sampling by clock rxd0 maximum one-cycle delay start bit baud rate generator clock rxd0 0 3 2 6 0 3 2 6 sampling timing unrss=1 unrss=0 count value = 7
ml610q407/ml610q408/ml610q409 user's manual chapter 13 uart 13-19 12.3.5.3 receive margin if there is an error between the sender baud rate and the baud ra te generated by the baud rate generator of this lsi, the error accumulates until the last stop bit lo ading in one frame, decreasing the receive margin. this receive margin needs to be fully considered, particularly when the baud rate generator clock uses a lower frequency such as lsclk and lsclk x 2 to realize a higher bit rate (e.g., 4800bps, 9600bps). figure 13-9 shows the baud rate errors and receive margin waveforms. figure 13-9 baud rate error and receive margin note: in system designing, ensure a suffici ent receive margin considering the ba ud rate difference between sender and receiver, start bit detection delay, distorti on in receive data, and influence of noise. sender baud rate is slow ( rxd0 ) sampling timing u0rss=1 u0rss=0 start start start sto p stop stop sender baud rate is fast ( rxd0 ) ideal waveform ( rxd0 )
ml610q407/ml610q408/ml610q409 user's manual chapter 13 uart 13-20 13.4 specifying port registers to enable the uart function, the applicab le bit of each related port register need s to be set. see chapter 21, ?port 4? and chapter 18, ?port 0? for detail about the port registers. 13.4.1 functioning p43(txd0) and p42(rxd0) as the uart set p43md1-p42md1 bits(bit3-bit2 of p4mod1 register) to ?0? and set p43md0-p42md0(bit3-bit2 of p4mod0 register) to ?1?, for specifying the uart as the secondary function of p43 and p42. register name p4mod1 register (address: 0f225h) bit 7 6 5 4 3 2 1 0 bit name p47md1 p46md1 p45md1 p44md1 p43md1 p42md1 p41md1 p40md1 setting value * * * * 0 0 * * register name p4mod0 register (address: 0f224h) bit 7 6 5 4 3 2 1 0 bit name p47md0 p46md0 p45md0 p44md0 p43md0 p42md0 p41md0 p40md0 setting value * * * * 1 1 * * set the p43c1 bit (p4con1 register's bit 3) to "1", the p43c0 bit (p4con0 register's bit 3) to "1", and the p43dir bit (p4dir register's bit 3) to "0" for specifying the state mode of the p43 pin to cmos output. set p42dir bit (bit2 of p4dir register) to ?1? for specifying the p42 as an input pin. the set value ($) is arbitrary for the p42c1 and p42c0 bits. select an arbitrary input mode depending on the state of the external circuit to which the p42 pin is connected. register name p4con1 register (address: 0f223h) bit 7 6 5 4 3 2 1 0 bit name p47c1 p46c1 p45c1 p44c1 p43c1 p42c1 p41c1 p40c1 setting value * * * * 1 $ * * register name p4con0 register (address: 0f222h) bit 7 6 5 4 3 2 1 0 bit name p47c0 p46c0 p45c0 p44c0 p43c0 p42c0 p41c0 p40c0 setting value * * * * 1 $ * * register name p4dir regi ster (address: 0f221h) bit 7 6 5 4 3 2 1 0 bit name p47dir p46dir p45dir p44dir p43dir p42dir p41dir p40dir setting value * * * * 0 1 * * the p43d to d42d bits (p4d register bits 3 to 2) da ta can either be "0" or "1 " (not need to be set). register name p4d register (address: 0f220h) bit 7 6 5 4 3 2 1 0 bit name p47d p46d p45d p44d p43d p42d p41d p40d setting value * * * * ** ** * * * : bit not related to the uart function ** : don?t care $: optional [note:] the receive pin (rxd) is selected by u0rsel bit (bit4 of ua0mod0 register). the initial value "0" selects the p02 and the value "1" selects the p43.
ml610q407/ml610q408/ml610q409 user's manual chapter 13 uart 13-21 13.4.2 functioning p43(txd0) and p02(rxd0) as the uart set p43md1 bit (bit3 of p4mod1 register) to ?0? and set p43md0(bit3 of p4mod0 register) to ?1?, for specifying the uart as the secondary function of p43. register name p4mod1 register (address: 0f225h) bit 7 6 5 4 3 2 1 0 bit name p47md1 p46md1 p45md1 p44md1 p43md1 p42md1 p41md1 p40md1 setting value * * * * 0 $ * * register name p4mod0 register (address: 0f224h) bit 7 6 5 4 3 2 1 0 bit name p47md0 p46md0 p45md0 p44md0 p43md0 p42md0 p41md0 p40md0 setting value * * * * 1 $ * * set the p43c1 bit (p4con1 register's bit 3) to "1", the p43c0 bit (p4con0 register's bit 3) to "1", and the p43dir bit (p4dir register's bit 3) to "0" for specifying the state mode of the p43 pin to cmos output. register name p4con1 register (address: 0f223h) bit 7 6 5 4 3 2 1 0 bit name p47c1 p46c1 p45c1 p44c1 p43c1 p42c1 p41c1 p40c1 setting value * * * * 1 * * * register name p4con0 register (address: 0f222h) bit 7 6 5 4 3 2 1 0 bit name p47c0 p46c0 p45c0 p44c0 p43c0 p42c0 p41c0 p40c0 setting value * * * * 1 * * * register name p4dir regi ster (address: 0f221h) bit 7 6 5 4 3 2 1 0 bit name p47dir p46dir p45dir p44dir p43dir p42dir p41dir p40dir setting value * * * * 0 * * * the p43d bit (p4d register bit 3) data can e ither be "0" or "1" (not need to be set). register name p4d register (address: 0f220h) bit 7 6 5 4 3 2 1 0 bit name p47d p46d p45d p44d p43d p42d p41d p40d setting value * * * * ** * * * the p02 pin is an input-only pin and does not need input/output selection by the register. the set value ($) is arbitrary for the p02c1 and p02c0 bits. select an arbitrary input mode depending on the state of the external circuit to which the p02 pin is connected. register name p0con1 register (address: 0f207h) bit 7 6 5 4 3 2 1 0 bit name - - - - p03c1 p02c1 p01c1 p00c1 setting value - - - - * $ * *
ml610q407/ml610q408/ml610q409 user's manual chapter 13 uart 13-22 register name p0con0 register (address: 0f206h) bit 7 6 5 4 3 2 1 0 bit name - - - - p03c0 p02c0 p01c0 p00c0 setting value - - - - * $ * * the p02d bit (p0d register bit 2) data can e ither be "0" or "1" (not need to be set). register name p0d register (address: 0f204h) bit 7 6 5 4 3 2 1 0 bit name - - - - p03d p02d p01d p00d setting value - - - - * ** * * - : bit that does not exist * : bit not related to the uart function ** : don?t care $: optional note: ?the receive pin (rxd) is selected by u0rsel bit (bit4 of ua0mod0 register). the initial value "0" selects the p02 and the value "1" selects the p43. ?even if the p42 pin is selected as rxd0 by the p42md1, p42md0, p42c1, p42c0, and p42idr bits, the p02 pin will be selected as rxd0 when the u0rsel bit of the ua0mod0 register is "0". ?p02(port 0) is an input-only port, does not have registers that can select data direction(input or output) or mode(primary or secondary function).
chapter 14 port 0
ml610q407/ml610q408/ml610q409 user's manual chapter 14 port 0 14-1 14. port 0 14.1 overview this lsi includes the 5-bit, input-only port 0 (p00 to p04). 14.1.1 features ? all bits support a maskable interrupt function. ? allows selection of interrupt disabled mode, falli ng-edge interrupt mode, rising-edge interrupt mode, or both-edge interrupt mode for each bit. ? allows selection of with/without interrupt sa mpling for each bit. (sampling frequency: t16khz) ? allows selection of high-impedance input mode, input mode with a pull-down resistor, or input mode with a pull-up resistor for each bit. ? the p00 and p01 pins can be used as the trigger input pi ns of the capture circuit and the p02 pin can be used as the rxd0 input pin of uart0. ? the p04 pin can be used as an external clock (t02p0ck) input pin for the timers and the pwm. 14.1.2 configuration figure 14-1 shows the configuration of port 0. p0d : port 0 data register p0con0 : port 0 control register 0 p0con1 : port 0 control register 1 exicon0 : external interrupt control register 0 exicon1 : external interrupt control register 1 exicon2 : external interrupt control register 2 figure 14-1 configuration of port 0 14.1.3 list of pins pin name i/o function p00/exi0/cap0 i input port, external 0 interrupt, capture 0 trigger signal input p01/exi1/cap1 i input port, external 1 interrupt, capture 1 trigger signal input p02/exi2/rxd0 i input port, external 2 interrupt, uart0 data input (rxd0) p03/exi3 i input port, external 3 interrupt p04/exi4/ t02p0ck i input port, external 4 interrupt, ex ternal clock input (t02p0ck) to timer 0, timer 2, and pwm0 data bus p 00 int to p 0 4int p 00 to p 0 4 p0con0 p0con1 interrupt controller v dd v dd v ss v ss 5 5 sampling clock t16khz rxd 0, t 0 2p 0c k 2 pull-up pull-down controller p0d exicon0 exicon1 exicon2
ml610q407/ml610q408/ml610q409 user's manual chapter 14 port 0 14-2 14.2 description of registers 14.2.1 list of registers address name symbol (byte) symbol (word) r/w size initial value 0f204h port 0 data register p0d ? r 8 depends on pin state 0f206h port 0 control regist er 0 p0con0 r/w 8/16 00h 0f207h port 0 control register 1 p0con1 p0con r/w 8 00h 0f020h external interrupt control register 0 exicon0 ? r/w 8 00h 0f021h external interrupt control register 1 exicon1 ? r/w 8 00h 0f022h external interrupt control register 2 exicon2 ? r/w 8 00h
ml610q407/ml610q408/ml610q409 user's manual chapter 14 port 0 14-3 14.2.2 port 0 data register (p0d) address: 0f204h access: r access size: 8-bit initial value: depends on pin state 7 6 5 4 3 2 1 0 p0d ? ? ? p04d p03d p02d p01d p00d r r r r r r r r r initial value 0 0 0 x x x x x p0d is a special function register (sfr) to only read the pin level of port 0. [description of bits] ? p04d to p00d (bits 4 to 0) the p04d to p00d bits are used to read the pin level of port 0. p04d description 0 p04 pin input: ?l? level 1 p04 pin input: ?h? level p03d description 0 p03 pin input: ?l? level 1 p03 pin input: ?h? level p02d description 0 p02 pin input: ?l? level 1 p02 pin input: ?h? level p01d description 0 p01 pin input: ?l? level 1 p01 pin input: ?h? level p00d description 0 p00 pin input: ?l? level 1 p00 pin input: ?h? level
ml610q407/ml610q408/ml610q409 user's manual chapter 14 port 0 14-4 14.2.3 port 0 control registers 0, 1 (p0con0, p0con1) address: 0f206h access: r/w access size: 8/16 bit initial value: 00h 7 6 5 4 3 2 1 0 p0con0 ? ? ? p04c0 p03c0 p02c0 p01c0 p00c0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 address: 0f207h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 p0con1 ? ? ? p04c1 p03c1 p02c1 p01c1 p00c1 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 p0con0 and p0con1 are special function registers (sfrs) to select the input mode of port 0. [description of bits] ? p04c0 to p00c0, p04c1 to p00c1 (bits 4 to 0) the p04c0 to p00c0 bits and the p04c1 to p00c1 bits are used to select high-impedance input mode, input mode with a pull-down resistor, or input mode with a pull-up resistor. the p0nc0 bit and the p0nc1 bit determine the input mode of p0n (example: when p02c0 = ?0? and p02c1 = ?1?, p02 is in input mode with a pull-up resistor). p04c1-p00c1 p04c0-p00c0 description 0 0 high-impedance input mode (initial value) 0 1 input mode with a pull-down resistor 1 0 input mode with a pull-up resistor 1 1 high-impedance input mode
ml610q407/ml610q408/ml610q409 user's manual chapter 14 port 0 14-5 14.2.4 external interrupt control registers 0, 1 (exicon0, exicon1) address: 0f020h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 exicon0 ? ? ? p04e0 p03e0 p02e0 p01e0 p00e0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 address: 0f021h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 exicon1 ? ? ? p04e1 p03e1 p02e1 p01e1 p00e1 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 exicon0 and exicon1 are special function registers (sfrs) to select an interrupt edge of port 0. [description of bits] ? p04e0 to p00e0 , p04e1 to p00e1 (bits 4 to 0) the p04e0 to p00e0 bits and the p04e1 to p00e1 bits ar e used to select interrupt disabled mode, falling-edge interrupt mode, rising-edge interrupt mode, or both-e dge interrupt mode. the p0ne0 bit and the p0ne1 bit determine the interrupt mode of p0n (example: when p02e0 = ?0? and p02e1 = ?1?, p02 is in rising-edge interrupt mode). p04e1-p00e1 p04e0-p00e0 description 0 0 interrupt disabled (initial value) 0 1 falling-edge interrupt mode 1 0 rising-edge interrupt mode 1 1 both-edge interrupt mode
ml610q407/ml610q408/ml610q409 user's manual chapter 14 port 0 14-6 14.2.5 external interrupt control register 2 (exicon2) address: 0f022h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 exicon2 ? ? ? p04sm p03sm p02sm p01sm p00sm r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 exicon2 is a special function register (sfr) to select whether the port 0 interrupt is with sampling or without sampling. [description of bits] ? p04sm to p00sm (bits 4 to 0) the p04sm to p00sm bits are used to select detection of signal edge for port 0 interrupts with or without sampling. the sampling clock is t16khz of the low-speed time base counter (ltbc). p04sm description 0 detects the input signal edge for a p04 interrupt without sampling (initial value). 1 detects the input signal edge for a p00 interrupt with sampling. p03sm description 0 detects the input signal edge for a p03 interrupt without sampling (initial value). 1 detects the input signal edge for a p00 interrupt with sampling. p02sm description 0 detects the input signal edge for a p02 interrupt without sampling (initial value). 1 detects the input signal edge for a p00 interrupt with sampling. p01sm description 0 detects the input signal edge for a p01 interrupt without sampling (initial value). 1 detects the input signal edge for a p00 interrupt with sampling. p00sm description 0 detects the input signal edge for a p00 interrupt without sampling (initial value). 1 detects the input signal edge for a p00 interrupt with sampling. note: in stop mode, since the 16 khz sampling clock stops, no sa mpling is performed regardless of the values set in p00sm to p04sm.
ml610q407/ml610q408/ml610q409 user's manual chapter 14 port 0 14-7 14.3 description of operation for each pin of port 0, the setting of the port 0 control registers 0 and 1 (p 0con0 and p0con1) a llows selection of high-impedance input mode, input mode with a pull-down resistor, or input mode with a pull-up resistor. high-impedance input mode is selected at system reset. the pin level of port 0 can be read by reading the port 0 data register (p0d). 14.3.1 external interrupt / secondary function the port 0 pins (p00, p01, p02, p03, p04) can be used fo r p00 to p04 interrupts (p00int to p04int). the p00 to p04 interrupts are maskable and interrupt enab le or disable can be selected. for interrupts, see chapter 5, "interrupt." the p00 and p01 pins can be used as the trigger input to the capture circuit, the p02 pin as the rxd0 input to the uart0, and the p04 pin as the external clock input to the timers and the pwm. for the capture function, see chapter 8, "capture." for the uart function, see chapter 13, "uart." for the timer function, see chapter 9, "timer." for the pwm function, see chapter 10, "pwm." 14.3.2 interrupt request when an interrupt edge selected with the external interrupt control register 0, 1, or 2 (exicon0, exicon1, or exicon2) occurs at a port 0 pin, any of the maskable p00 to p04 interrupts (p00int to p04int) occurs. figure 14-2 shows the p00 to p04 interrupt generation timing in rising-edge interrupt mode, in falling-edge interrupt mode, and in both-edge interrupt mode without sampling and the p00 to p04 interrupt generation timing in rising-edge interrupt mode with sampling. (a) when falling-edge interrupt mode without sampling is selected (b) when rising-edge interrupt mode without sampling is selected (c) when both-edge interrupt mode without sampling is selected sysclk p0n pin p0nint interrupt request qp0n sysclk p0n pin p0nint interrupt request qp0n sysclk p0n pin p0nint interrupt request qp0n
ml610q407/ml610q408/ml610q409 user's manual chapter 14 port 0 14-8 (d) when rising-edge interrupt mode with sampling is selected figure 14-2 p00 to p04 interrupts generation timing sysclk p0n pin p0nint interrupt request qp0n n = 0,1,2,3,4 t16khz
chapter 15 port 2
ml610q407/ml610q408/ml610q409 user's manual chapter 15 port 2 15-1 15. port 2 15.1 overview this lsi includes 4-bit port 2 (p20 to p22, and p24) dedicated to output. port 2 can output low-speed clock (lsclk), high-speed cl ock (outclk), melody, and pwm waveform as a secondary function. for the clock output, see chapter 6, "clock generation circuit." for the melody 0 (md0) output, see chapter 20, "melody driver." for the pwm (pwm0) output, see chapter 10, "pwm." 15.1.1 features ? allows direct led drive. ? allows selection of high-impedance output mode, p-channel open drain output mode, n-channel open drain output mode, or cmos out put mode for each bit. ? allows output of low-speed clock (lsclk), high-speed clock (outclk), melody 0 (md0), and pmw waveform (pwm0) as a secondary function. 15.1.2 configuration figure 15-1 shows the configuration of port 2. p2d : port 2 data register p2con0 : port 2 control register 0 p2con1 : port 2 control register 1 p2mod : port 2 mode register figure 15-1 configuration of port 2 15.1.3 list of pins pin name i/o primary function secondary function p20/led0/lsclk o output port low-speed clock output (lsclk) p21/led1/outclk o output port high-speed clock output (outclk) p22/led2/md0 o output port melody 0 output (md0) p24/led4/pwm0 o output port pwm0 output (pwm0) data bus lsclk outclk md0 pwm0 p2 0 to p22 , p24 p2mod p2con0 p2con1 v dd v dd v ss v ss 4 4 port2 output controller p2d
ml610q407/ml610q408/ml610q409 user's manual chapter 15 port 2 15-2 15.2 description of registers 15.2.1 list of registers address name symbol (byte) symbol (word) r/w size initial value 0f210h port 2 data register p2d ? r/w 8 00h 0f212h port 2 control regist er 0 p2con0 r/w 8/16 00h 0f213h port 2 control register 1 p2con1 p2con r/w 8 00h 0f214h port 2 mode register p2mod ? r/w 8 00h
ml610q407/ml610q408/ml610q409 user's manual chapter 15 port 2 15-3 15.2.2 port 2 data register (p2d) address: 0f210h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 p2d ? ? ? p24d ? p22d p21d p20d r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 p2d is a special function register (sfr) to set the output value of the port 2. the value of this register is output to port 2. the value written to p2d is readable. [description of bits] ? p24d (bits 4 to 0) the p24d and p22d to p20d bits are used to set the output value of the port 2 pin. p24d description 0 output level of the p24 pin: "l" 1 output level of the p24 pin: "h" p22d description 0 output level of the p22 pin: ?l? 1 output level of the p22 pin: ?h? p21d description 0 output level of the p21 pin: ?l? 1 output level of the p21 pin: ?h? p20d description 0 output level of the p20 pin: ?l? 1 output level of the p20 pin: ?h?
ml610q407/ml610q408/ml610q409 user's manual chapter 15 port 2 15-4 15.2.3 port 2 control registers 0, 1 (p2con0, p2con1) address: 0f212h access: r/w access size: 8/16 bit initial value: 00h 7 6 5 4 3 2 1 0 p2con0 ? ? ? p24c0 ? p22c0 p21c0 p20c0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 address: 0f213h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 p2con1 ? ? ? p24c1 ? p22c1 p21c1 p20c1 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 p2con0 and p2con1 are special function registers (sfrs) to select the output state of the output pin port 2. [description of bits] ? p24c0, p22c0 to p20c0, p24c1, p22c1 to p20c1 (bits 4 and 2 to 0) the p24c0, p22c0 to p20c0, p24c1, and p22c1 to p20c 1 bits are used to select high-impedance output mode, p-channel open drain output mode, n-channel ope n drain output mode, or cmos output mode. to directly drive leds, select n-channel open drain output mode. p24c1 p24c0 description 0 0 p24 pin: in high-impedance output mode (initial value) 0 1 p24 pin: in p-channel open drain output mode 1 0 p24 pin: in n-channel open drain output mode 1 1 p24 pin: in cmos output mode p22c1 p22c0 description 0 0 p22 pin: in high-impedance output mode (initial value) 0 1 p22 pin: in p-channel open drain output mode 1 0 p22 pin: in n-channel open drain output mode 1 1 p22 pin: in cmos output mode p21c1 p21c0 description 0 0 p21 pin: in high-impedance output mode (initial value) 0 1 p21 pin: in p-channel open drain output mode 1 0 p21 pin: in n-channel open drain output mode 1 1 p21 pin: in cmos output mode p20c1 p20c0 description 0 0 p20 pin: in high-impedance output mode (initial value) 0 1 p20 pin: in p-channel open drain output mode 1 0 p20 pin: in n-channel open drain output mode 1 1 p20 pin: in cmos output mode
ml610q407/ml610q408/ml610q409 user's manual chapter 15 port 2 15-5 15.2.4 port 2 mode register (p2mod) address: 0f214h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 p2mod ? ? ? p24md ? p22md p21md p20md r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 p2mod is a special function register (sfr) to select the primary function or the secondary function of port 2. [description of bits] ? p24md (bit 4) the p24md bit is used to select the primary function or the secondary function of the p24 pin. p24md description 0 general-purpose output port function (initial value) 1 pwm0 output function ? p22md (bit 2) the p22md bit is used to select the primary function or the secondary function of the p22 pin. p22md description 0 general-purpose output port function (initial value) 1 melody 0 (md0) output function ? p21md (bit 1) the p21md bit is used to select the primary function or the secondary function of the p21 pin. p21md description 0 general-purpose output port function (initial value) 1 high-speed clock (outclk) output function ? p20md (bit 0) the p20md bit is used to select the primary function or the secondary function of the p20 pin. p20md description 0 general-purpose output port function (initial value) 1 low-speed clock (lsclk) output function note: z p2 (port 2) is an output-only pin and does not have the re gister to select the data direction(input or output). z the output characteristics of the p2 pins (p20, p21, p 22, and p24) are vol1 and voh1 (described in "appendix c electrical characteristics") when each bit (p20md, p21md, p22md, and p24md) of the corresponding p2mod register is "1" (melody/buzzer is sel ected as the secondary function) and ar e vol2 and voh2 when each bit is "0".
ml610q407/ml610q408/ml610q409 user's manual chapter 15 port 2 15-6 15.3 description of operation 15.3.1 output port function for each pin of port 2, any one of high-impedance output mode, p-channel open drain output m ode, n-channel open drain output mode, and cmos output mode can be selected by setting the port 2 control registers 0 and 1 (p2con0 and p2con1). at a system reset, high-impedance output mode is selected as the initial state. depending of the value set in the port 2 da ta register (p2d), a ?l? level or ?h? le vel signal is output to each pin of port 2. 15.3.2 secondary function low-speed clock (lsclk) output, high-speed clock (outclk) output, melody 0 (md0) output, and pwm 0 output are assigned to port 2 as a secondary function. the secondary func tion can be used by setti ng the p24md and p22md to p20md bits of the port 2 mode register (p2mod) to ?1?.
chapter 16 port 3
ml610q407/ml610q408/ml610q409 user's manual chapter 16 port 3 16-1 16. port 3 16.1 overview this lsi includes port 3 (p30 to p35), which is a 6-bit input/output port. furthermore, the oscillation pins (in0, cs0, rs0, rt0, rct0, and rcm) for the rc-adc (channel 0) are provided as the secondary function mode. for the rc-adc, see chapter 21, ?rc oscillation type a/d converter?. 16.1.1 features ? allows selection of high-impedance output, p-channe l open drain output, n-channel open drain output, or cmos output for each bit in output mode. ? allows selection of high-impedance input, input with a pull-down resistor, or input with a pull-up resistor for each bit in input mode. ? the oscillation pins (in0, cs0, rs0, rt0, rct0, and rcm) for the rc-adc (channel 0) are available as the secondary function mode. 16.1.2 configuration figure 16-1 shows the configuration of port 3. p3d : port 3 data register p3dir : port 3 direction register p3con0 : port 3 control register 0 p3con1 : port 3 control register 1 p3mod0 : port 3 mode register 0 figure 16-1 configuration of port 3 16.1.3 list of pins pin name i/o primary function secondary function p30/in0 i/o input/output port oscillati on waveform input pin for rc-adc0 p31/cs0 i/o input/output port reference capacitor connection pin for rc-adc0 p32/rs0 i/o input/output port reference resistor connection pin for rc-adc0 p33/rt0 i/o input/output port resistor sensor connecti on pin for measurement for rc-adc0 p34/rct0 i/o input/output port resistor/capacitor sensor connection pin for measurement for rc-adc0 p35/rcm i/o input/output port rc osc illation monitor pin for rc-adc0 data bus output for rc-adc (cs0, rs0, rt0, rct0, rcm) p30 to p35 p3dir p3mod0 p3con0,1 v dd v dd v ss v ss 6 5 port3 output controller p3d v dd v ss pull-up pull-down controller input for rc-adc (in0) 1 6
ml610q407/ml610q408/ml610q409 user's manual chapter 16 port 3 16-2 16.2 description of registers 16.2.1 list of registers address name symbol (byte) symbol (word) r/w size initial value 0f218h port 3 data register p3d ? r/w 8 00h 0f219h port 3 direction r egister p3dir ? r/w 8 00h 0f21ah port 3 control regist er 0 p3con0 r/w 8/16 00h 0f21bh port 3 control register 1 p3con1 p3con r/w 8 00h 0f21ch port 3 mode register 0 p3mod0 ? r/w 8 00h
ml610q407/ml610q408/ml610q409 user's manual chapter 16 port 3 16-3 16.2.2 port 3 data register (p3d) address: 0f218h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 p3d ? ? p35d p34d p33d p32d p31d p30d r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 p3d is a special function register (sfr) to set the value to be output to the port 3 pin or to read the input level of the port 3. in output mode, the value of this register is output to the port 3 pin. the value written to p3d is readable. in input mode, the input level of the port 3 pin is read when p3d is read. output mode or input mode is selected by using the port direction register (p3dir) described later. [description of bits] ? p35d to p30d (bits 5 to 0) the p35d to p30d bits are used to set the output value of the port 3 pin in output mode and to read the pin level of the port 3 pin in input mode. p35d description 0 output or input leve l of the p35 pin: ?l? 1 output or input leve l of the p35 pin: ?h? p34d description 0 output or input leve l of the p34 pin: ?l? 1 output or input leve l of the p34 pin: ?h? p33d description 0 output or input leve l of the p33 pin: ?l? 1 output or input leve l of the p33 pin: ?h? p32d description 0 output or input leve l of the p32 pin: ?l? 1 output or input leve l of the p32 pin: ?h? p31d description 0 output or input leve l of the p31 pin: ?l? 1 output or input leve l of the p31 pin: ?h? p30d description 0 output or input leve l of the p30 pin: ?l? 1 output or input leve l of the p30 pin: ?h?
ml610q407/ml610q408/ml610q409 user's manual chapter 16 port 3 16-4 16.2.3 port 3 direction register (p3dir) address: 0f219h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 p3dir ? ? p35dir p34dir p33dir p32dir p31dir p30dir r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 p3dir is a special function register (sfr) to select the input/output mode of port 3. [description of bits] ? p35dir to p30dir (bits 5 to 0) p35dir to p30dir are the bits for setting the input/output direction of the port 3 pins. p35dir description 0 p35 pin: output (initial value) 1 p35 pin: input p34dir description 0 p34 pin: output (initial value) 1 p34 pin: input p33dir description 0 p33 pin: output (initial value) 1 p33 pin: input p32dir description 0 p32 pin: output (initial value) 1 p32 pin: input p31dir description 0 p31 pin: output (initial value) 1 p31 pin: input p30dir description 0 p30 pin: output (initial value) 1 p30 pin: input
ml610q407/ml610q408/ml610q409 user's manual chapter 16 port 3 16-5 16.2.4 port 3 control registers 0, 1 (p3con0, p3con1) address: 0f21ah access: r/w access size: 8/16 bit initial value: 00h 7 6 5 4 3 2 1 0 p3con0 ? ? p35c0 p34c0 p33c0 p32c0 p31c0 p30c0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 address: 0f21bh access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 p3con1 ? ? p35c1 p34c1 p33c1 p32c1 p31c1 p30c1 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 p3con0 and p3con1 are special function registers (sfrs) to select input/output state of the port 3 pin. the input/output state is different between input mode and output mode. input or output is selected by using the p3dir register. [description of bits] ? p35c1 to p30c1, p35c0 to p30c0 (bits 5 to 0) p35c1 to p30c1 and p35c0 to p30c0 are the bit bits for selecting the high-impedance output, p-channel open drain output, n-channel open drain output, or cmos output in output mode and for selecting the high-impedance input, input with a pull-down resistor, or input with a pull-up resistor in input mode. setting of p35 pin when output mode is selected (p35dir bit = ?0?) when input mode is selected (p35dir bit = ?1?) p35c1 p35c0 description 0 0 p35 pin: high-impedance output (initial value) p35 pin: high-impedance input 0 1 p35 pin: p-channel open dr ain output p35 pin: input with a pull-down resistor 1 0 p35 pin: n-channel open drain output p 35 pin: input with a pull-up resistor 1 1 p35 pin: cmos output p35 pin: high-impedance input setting of p34 pin when output mode is selected (p34dir bit = ?0?) when input mode is selected (p34dir bit = ?1?) p34c1 p34c0 description 0 0 p34 pin: high-impedance output (initial value) p34 pin: high-impedance input 0 1 p34 pin: p-channel open dr ain output p34 pin: input with a pull-down resistor 1 0 p34 pin: n-channel open drain output p 34 pin: input with a pull-up resistor 1 1 p34 pin: cmos output p34 pin: high-impedance input
ml610q407/ml610q408/ml610q409 user's manual chapter 16 port 3 16-6 setting of p33 pin when output mode is selected (p33dir bit = ?0?) when input mode is selected (p33dir bit = ?1?) p33c1 p33c0 description 0 0 p33 pin: high-impedance output (initial value) p33 pin: high-impedance input 0 1 p33 pin: p-channel open dr ain output p33 pin: input with a pull-down resistor 1 0 p33 pin: n-channel open drain output p 33 pin: input with a pull-up resistor 1 1 p33 pin: cmos output p33 pin: high-impedance input setting of p32 pin when output mode is selected (p32dir bit = ?0?) when input mode is selected (p32dir bit = ?1?) p32c1 p32c0 description 0 0 p32 pin: high-impedance output (initial value) p32 pin: high-impedance input 0 1 p32 pin: p-channel open dr ain output p32 pin: input with a pull-down resistor 1 0 p32 pin: n-channel open drain output p 32 pin: input with a pull-up resistor 1 1 p32 pin: cmos output p32 pin: high-impedance input setting of p31 pin when output mode is selected (p31dir bit = ?0?) when input mode is selected (p31dir bit = ?1?) p31c1 p31c0 description 0 0 p31 pin: high-impedance output (initial value) p31 pin: high-impedance input 0 1 p31 pin: p-channel open dr ain output p31 pin: input with a pull-down resistor 1 0 p31 pin: n-channel open drain output p 31 pin: input with a pull-up resistor 1 1 p31 pin: cmos output p31 pin: high-impedance input setting of p30 pin when output mode is selected (p30dir bit = ?0?) when input mode is selected (p30dir bit = ?1?) p30c1 p30c0 description 0 0 p30 pin: high-impedance output (initial value) p30 pin: high-impedance input 0 1 p30 pin: p-channel open dr ain output p30 pin: input with a pull-down resistor 1 0 p30 pin: n-channel open drain output p 30 pin: input with a pull-up resistor 1 1 p30 pin: cmos output p30 pin: high-impedance input
ml610q407/ml610q408/ml610q409 user's manual chapter 16 port 3 16-7 16.2.5 port 3 mode register 0 (p3mod0) address: 0f21ch access: r/w access size: 8/16 bit initial value: 00h 7 6 5 4 3 2 1 0 p3mod0 ? ? p35md0 p34md0 p33md0 p 32md0 p31md0 p30md0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 p3mod0 is a special function register (sfr) to select the primary function or the secondary function of port 3. [description of bits] ? p35md0 (bit 5) the p35md0 bit is used to select the primary or secondary function of the p35 pin. p35md0 description 0 general-purpose input/output mode (initial value) 1 rc oscillation monitor pin for rc-adc ? p34md0 (bit 4) the p34md0 bit is used to select the primary function or the secondary function of the p34 pin. p34md0 description 0 general-purpose input/output mode (initial value) 1 resistor/capacitor sensor connecti on pin for measurement for rc-adc (channel 0) ? p33md0 (bit 3) the p33md0 bit is used to select the primary or secondary function of the p33 pin. p33md0 description 0 general-purpose input/output mode (initial value) 1 resistor/capacitor sensor connecti on pin for measurement for rc-adc (channel 0) ? p32md0 (bit 2) the p32md0 bit is used to select the primary or secondary function of the p32 pin. p32md0 description 0 general-purpose input/output mode (initial value) 1 reference resistor connection pin for rc-adc (channel 0) ? p31md0 (bit 1) the p31md0 bit is used to select the primary or secondary function of the p31 pin. p31md0 description 0 general-purpose input/output mode (initial value) 1 reference capacitor connecti on pin for rc-adc (channel 0)
ml610q407/ml610q408/ml610q409 user's manual chapter 16 port 3 16-8 ? p30md0 (bit 0) the p30md0 bit is used to select the primary or secondary function of the p30 pin. p30md0 description 0 general-purpose input/output mode (initial value) 1 rc oscillation waveform input pin for rc-adc (channel 0) note: when using the rc-adc as the secondary function, set th e p3dir, p3con0, and p3con1 registers to bring each pin state to high-impedance i nput (same for when using the rc oscillation monitor function). pull-up or pull-down input makes drawing the current.
ml610q407/ml610q408/ml610q409 user's manual chapter 16 port 3 16-9 16.3 description of operation 16.3.1 input/output port functions for each pin of port 3, either output or input is selected by setting the port 3 direction re gister (p3dir). in output mode, high-impedance output mode, p-channel open drain output mode, n-channel open drain output mode, or cmos output mode can be selected by setting the port 3 control registers 0 and 1 (p3con0 and p3con1). in input mode, high-impedance input mode, input mode with a pull-down resistor, or input mode with a pull-up resistor can be selected by setting the port 3 control registers 0 and 1 (p3con0 and p3con1). at a system reset, high-impedance output mode is selected as the initial state. in output mode, ?l? or ?h? level is output to each pin of port 3 depending on the va lue set by the port 3 data register (p3d). in input mode, the input level of each pin of port 3 can be read from the port 3 data register (p3d). 16.3.2 secondary function the secondary function is assigned to po rt 3 as the rc-adc (channel 0) oscillati on pins (in0, cs0, rs0, rt0, crt0, rcm). each of them can be used as the secondary function by setting the p35md0 to p30md0 bits of the port 3 mode register (p3mod0). note: ? all the port 3 pins except p35/rcm are configured as pins dedicated to the rc-adc function during a/d conversion. therefore, if there is any unused pin, that pin cannot be used as its primary function during a/d conversion. for the rc-adc, see chapter 21, ?rc osc illation type a/d converter?.
chapter 17 port 4
ml610q407/ml610q408/ml610q409 user's manual chapter 17 port 4 17-1 17. port 4 17.1 overview this lsi includes port 4 (p40 to p47) which is an 8-bit input/output port. this port 4 can have the uart, rc-adc, synchronous serial port, and pwm output functions as the secondary and tertiary functions. for the uart, see chapter 13, "uart." for the rc-adc, s ee chapter 21, "rc oscillation type a/d converter." for the synchronous serial port, see chapter 12, "synchronous serial port." for the pwm, see chapter 10, "pwm." 17.1.1 features ? allows selection of high-impedance output, p-channe l open drain output, n-channel open drain output, or cmos output for each bit in output mode. ? allows selection of high-impedance input, input with a pull-down resistor, or input with a pull-up resistor for each bit in input mode. ? the p44 pin can be used as the external clock input pin for the timer 0 and timer 2 and the pwm0. the p45 pin can be used as the external clock input pin for the timer 1 and timer 3. ? the uart pins (rxd0, txd0), rc-adc (channel 1) oscillation pins (in1, cs1, rs1, rt1), synchronous serial port pins (sin0, sck0, sout0), and pwm output pin (pwm0) can be used as the secondary functions. 17.1.2 configuration figure 17-1 shows the configuration of port 4. p4d : port 4 data register p4dir : port 4 direction register p4con0 : port 4 control register 0 p4con1 : port 4 control register 1 p4mod0 : port 4 mode register 0 p4mod1 : port 4 mode register 1 figure 17-1 configuration of port 4 data bus output for uart (txd0) output for rc-adc (cs1, rs1, rt1) output for sio (sck0, sout0) output for pwm (pwm0) p4 0 to p47 p4dir p4mod0,1 p4con0,1 v dd v dd v ss v ss 8 7 port4 output controller p4d v dd v ss pull-up pull-down controller input/output for uart (rxd0) input for rc-adc (in1) input for sio (sin0, sck0) input for timer/pwm (t02p0ck, t13ck) 6 8
ml610q407/ml610q408/ml610q409 user's manual chapter 17 port 4 17-2 17.1.3 list of pins pin name i/o primary function sec ondary function tertiary function p40/sin0 i/o input/output port ? ssio0 data input pin p41/sck0 i/o input/output port ? ssio0 clock input/output pin p42/rxd0/sout0 i/o input/output port uart 0 data input pin ssio0 data output pin p43/txd0/pwm0 i/o input/output port ua rt0 data output pin pwm0 output pin p44/ t0p02ck /in1/sin0 i/o input/output port, timer0/timer2/ pwm0 external clock input rc oscillation waveform input pin for rc-adc1 ssio0 data input pin p45/ t13ck /cs1/sck0/ i/o input/output port, timer 1/ timer 3 external clock input reference capacitor connection pin for rc-adc1 ssio0 clock input/output pin p46/rs1/sout0 i/o input/output port reference resistor connection pin for rc-adc1 ssio0 data output pin p47/rt1 i/o input/output port resistor sensor connection pin for measurement for rc-adc1 ?
ml610q407/ml610q408/ml610q409 user's manual chapter 17 port 4 17-3 17.2 description of registers 17.2.1 list of registers address name symbol (byte) symbol (word) r/w size initial value 0f220h port 4 data register p4d ? r/w 8 00h 0f221h port 4 direction r egister p4dir ? r/w 8 00h 0f222h port 4 control regist er 0 p4con0 r/w 8/16 00h 0f223h port 4 control register 1 p4con1 p4con r/w 8 00h 0f224h port 4 mode register 0 p4mod0 r/w 8/16 00h 0f225h port 4 mode register 1 p4mod1 p4mod r/w 8 00h
ml610q407/ml610q408/ml610q409 user's manual chapter 17 port 4 17-4 17.2.2 port 4 data register (p4d) address: 0f220h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 p4d p47d p46d p45d p44d p43d p42d p41d p40d r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 p4d is a special function register (sfr) to set the value to be output to the port 4 pin or to read the input level of the port 4. in output mode, the value of this register is output to the port 4 pin. the value written to p4d is readable. in input mode, the input level of the port 4 pin is read when p4d is read. output mode or input mode is selected by using the port direction register (p4dir) described later. [description of bits] ? p47d to p40d (bits 7 to 0) the p47d to p40d bits are used to set the output value of the port 4 pin in output mode and to read the pin level of the port 4 pin in input mode. p47d description 0 output or input leve l of the p47 pin: ?l? 1 output or input leve l of the p47 pin: ?h? p46d description 0 output or input leve l of the p46 pin: ?l? 1 output or input leve l of the p46 pin: ?h? p45d description 0 output or input leve l of the p45 pin: ?l? 1 output or input leve l of the p45 pin: ?h? p44d description 0 output or input leve l of the p44 pin: ?l? 1 output or input leve l of the p44 pin: ?h? p43d description 0 output or input leve l of the p43 pin: ?l? 1 output or input leve l of the p43 pin: ?h? p42d description 0 output or input leve l of the p42 pin: ?l? 1 output or input leve l of the p42 pin: ?h? p41d description 0 output or input leve l of the p41 pin: ?l? 1 output or input leve l of the p41 pin: ?h? p40d description 0 output or input leve l of the p40 pin: ?l? 1 output or input leve l of the p40 pin: ?h?
ml610q407/ml610q408/ml610q409 user's manual chapter 17 port 4 17-5 17.2.3 port 4 direction register (p4dir) address: 0f221h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 p4dir p47dir p46dir p45dir p44dir p43dir p42dir p41dir p40dir r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 p4dir is a special function register (sfr) to select the input/output mode of port 4. [description of bits] ? p47dir to p40dir (bits 7 to 0) p47dir to p40dir are the bits for selecting the input/output mode of the port 4 pins. p47dir description 0 p47 pin: output (initial value) 1 p47 pin: input p46dir description 0 p46 pin: output (initial value) 1 p46 pin: input p45dir description 0 p45 pin: output (initial value) 1 p45 pin: input p44dir description 0 p44 pin: output (initial value) 1 p44 pin: input p43dir description 0 p43 pin: output (initial value) 1 p43 pin: input p42dir description 0 p42 pin: output (initial value) 1 p42 pin: input p41dir description 0 p41 pin: output (initial value) 1 p41 pin: input p40dir description 0 p40 pin: output (initial value) 1 p40 pin: input
ml610q407/ml610q408/ml610q409 user's manual chapter 17 port 4 17-6 17.2.4 port 4 control registers 0, 1 (p4con0, p4con1) address: 0f222h access: r/w access size: 8/16 bit initial value: 00h 7 6 5 4 3 2 1 0 p4con0 p47c0 p46c0 p45c0 p44c0 p43c0 p42c0 p41c0 p40c0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 address: 0f223h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 p4con1 p47c1 p46c1 p45c1 p44c1 p43c1 p42c1 p41c1 p40c1 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 p4con0 and p4con1 are special function registers (sfrs) to select input/output state of the port 4 pin. the input/output state is different between input mode and output mode. input or output is selected by using the p4dir register. [description of bits] ? p47c1 to p40c1, p47c0 to p40c0 (bits 7 to 0) p47c1 to p40c1 and p47c0 to p40c0 are the bits fo r selecting the high-impedance output, p-channel open drain output, n-channel open drain output, or cmos output in output mode and for selecting the high-impedance input, input with a pull-down resistor, or input with a pull-up resistor in input mode. setting of p47 pin when output mode is selected (p47dir bit = ?0?) when input mode is selected (p47dir bit = ?1?) p47c1 p47c0 description 0 0 high-impedance output (initial value) high-impedance input 0 1 p-channel open drain output input with a pull-down resistor 1 0 n-channel open drain output i nput with a pull-up resistor 1 1 cmos output high-impedance input setting of p46 pin when output mode is selected (p46dir bit = ?0?) when input mode is selected (p46dir bit = ?1?) p46c1 p46c0 description 0 0 high-impedance output (initial value) high-impedance input 0 1 p-channel open drain output input with a pull-down resistor 1 0 n-channel open drain output i nput with a pull-up resistor 1 1 cmos output high-impedance input
ml610q407/ml610q408/ml610q409 user's manual chapter 17 port 4 17-7 setting of p45 pin when output mode is selected (p45dir bit = ?0?) when input mode is selected (p45dir bit = ?1?) p45c1 p45c0 description 0 0 high-impedance output (initial value) high-impedance input 0 1 p-channel open drain output input with a pull-down resistor 1 0 n-channel open drain output i nput with a pull-up resistor 1 1 cmos output high-impedance input setting of p44 pin when output mode is selected (p44dir bit = ?0?) when input mode is selected (p44dir bit = ?1?) p44c1 p44c0 description 0 0 high-impedance output (initial value) high-impedance input 0 1 p-channel open drain output input with a pull-down resistor 1 0 n-channel open drain output i nput with a pull-up resistor 1 1 cmos output high-impedance input setting of p43 pin when output mode is selected (p43dir bit = ?0?) when input mode is selected (p43dir bit = ?1?) p43c1 p43c0 description 0 0 high-impedance output (initial value) high-impedance input 0 1 p-channel open drain output input with a pull-down resistor 1 0 n-channel open drain output i nput with a pull-up resistor 1 1 cmos output high-impedance input setting of p42 pin when output mode is selected (p42dir bit = ?0?) when input mode is selected (p42dir bit = ?1?) p42c1 p42c0 description 0 0 high-impedance output (initial value) high-impedance input 0 1 p-channel open drain output input with a pull-down resistor 1 0 n-channel open drain output i nput with a pull-up resistor 1 1 cmos output high-impedance input setting of p41 pin when output mode is selected (p41dir bit = ?0?) when input mode is selected (p41dir bit = ?1?) p41c1 p41c0 description 0 0 high-impedance output (initial value) high-impedance input 0 1 p-channel open drain output input with a pull-down resistor 1 0 n-channel open drain output i nput with a pull-up resistor 1 1 cmos output high-impedance input setting of p40 pin when output mode is selected (p40dir bit = ?0?) when input mode is selected (p40dir bit = ?1?) p40c1 p40c0 description 0 0 high-impedance output (initial value) high-impedance input 0 1 p-channel open drain output input with a pull-down resistor 1 0 n-channel open drain output i nput with a pull-up resistor 1 1 cmos output high-impedance input
ml610q407/ml610q408/ml610q409 user's manual chapter 17 port 4 17-8 17.2.5 port 4 mode registers 0, 1 (p4mod0, p4mod1) address: 0f224h access: r/w access size: 8/16 bit initial value: 00h 7 6 5 4 3 2 1 0 p4mod0 p47md0 p46md0 p45md0 p44md0 p43md0 p42md0 p41md0 p40md0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 address: 0f225h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 p4mod1 p47md1 p47md1 p45md1 p44md1 p43md1 p42md1 p41md1 p40md1 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 p4mod0 and p4mod1 are special function registers (sfrs) to select the primary, secondary, or tertiary function of port 4. [description of bits] ? p47md1, p47md0 (bit 7) the p47md1 and p47md0 bits are used to select the primary or secondary function of the p47 pin. p47md1 p47md0 description 0 0 general-purpose input/out put mode (initial value) 0 1 resistor sensor connection pin for measurement for rc-adc (channel 1) 1 0 prohibited 1 1 prohibited ? p46md1, p46md0 (bit 6) the p46md1 and p46md0 bits are used to select the primary, secondary, or tertiary function of the p46 pin. p46md1 p46md0 description 0 0 general-purpose input/out put mode (initial value) 0 1 reference resistor connection pin for rc-adc (channel 1) 1 0 sio0 data output pin 1 1 prohibited ? p45md1, p45md0 (bit 5) the p45md1 and p45md0 bits are used to select the primary, secondary, or tertiary function of the p45 pin. p45md1 p45md0 description 0 0 general-purpose input/out put mode (initial value) 0 1 reference capacitor connec tion pin for rc-adc (channel 1) 1 0 sio0 clock input/output pin 1 1 prohibited
ml610q407/ml610q408/ml610q409 user's manual chapter 17 port 4 17-9 ? p44md1, p44md0 (bit 4) the p44md1 and p44md0 bits are used to select the primary, secondary, or tertiary function of the p44 pin. p44md1 p44md0 description 0 0 general-purpose input/out put mode (initial value) 0 1 rc oscillation waveform input pin for rc-ad (channel 1) 1 0 sio0 data input pin 1 1 prohibited ? p43md1, p43md0 (bit 3) the p43md1 and p43md0 bits are used to select the primary, secondary, or tertiary function of the p43 pin. p43md1 p43md0 description 0 0 general-purpose input/out put mode (initial value) 0 1 uart0 data output pin 1 0 pwm0 output pin 1 1 prohibited ? p42md1, p42md0 (bit 2) the p42md1 and p42md0 bits are used to select the primary, secondary, or tertiary function of the p42 pin. p42md1 p42md0 description 0 0 general-purpose input/out put mode (initial value) 0 1 uart0 data input pin 1 0 sio0 data output pin 1 1 prohibited ? p41md1, p41md0 (bit 1) the p41md1 and p41md0 bits are used to select the primary or tertiary function of the p41 pin. p41md1 p41md0 description 0 0 general-purpose input/out put mode (initial value) 0 1 prohibited 1 0 sio0 clock input/output pin 1 1 prohibited ? p40md1, p40md0 (bit 0) the p40md1 and p40md0 bits are used to select the primary or tertiary function of the p40 pin. p40md1 p40md0 description 0 0 general-purpose input/out put mode (initial value) 0 1 prohibited 1 0 sio0 data input pin 1 1 prohibited note: when the pin is set to "prohibited" and the output mode is selected (by the port 4 control register), the port 4 output pin state is fixed as follows regardless of the data of the port data register p4d: when high-impedance output is selected: output pin is high-impedance when p-channel open drain output is selected: output pin is high-impedance when n-channel open drain output is selected: output pin is fixed to "l" when cmos output is selected: output pin is fixed to "l"
ml610q407/ml610q408/ml610q409 user's manual chapter 17 port 4 17-10 when using the rc-adc as the secondary function, set th e p4dir, p4con0, and p4con1 registers to bring each pin state to high-impedance input. pull-up or pull-down input makes drawing the current. when using the p44 pin as sio0 data input, set the p40 pin not to be thertialy function in the p4mod0 and p4mod1 registers.
ml610q407/ml610q408/ml610q409 user's manual chapter 17 port 4 17-11 17.3 description of operation 17.3.1 input/output port functions for each pin of port 4, either output or input is selected by setting the port 4 direction re gister (p4dir). in output mode, high-impedance output mode, p-channel open drain output mode, n-channel open drain output mode, or cmos output mode can be selected by setting the port 4 control registers 0 and 1 (p4con0 and p4con1). in input mode, high-impedance input mode, input mode with a pull-down resistor, or input mode with a pull-up resistor can be selected by setting the port 4 control registers 0 and 1 (p4con0 and p4con1). at a system reset, high-impedance output mode is selected as the initial state. in output mode, ?l? or ?h? level is output to each pin of port 4 depending on the va lue set by the port 4 data register (p4d). in input mode, the input level of each pin of port 4 can be read from the port 4 data register (p4d). 17.3.2 secondary and tertiary functions the secondary and tertiary functions are assigned to port 4 as the uart0 pins (rxd0, txd0), rc-adc (channel 1) oscillation pins (in1, cs1, rs1, rt1) , synchronous serial port 0 pins (sin0, sck0, sout), and the pwm output pin (pwm0). these pins can be used in a secondary or tertiary function mode by setting the p47md0 to p40md0 bits and the p47md1 to p40md1 bits of the port 4 mode registers (p4mod0, p4mod1). note: the p44 to p47 pins of port 4 are configured as pins dedicated to the rc-adc function during a/d conversion. therefore, if any of them is unused, it cannot be used as the primary function (or as the port). for the rc-adc, see chapter 21, ?rc oscillati on type a/d converter?.
chapter 18 port 5
ml610q407/ml610q408/ml610q409 user's manual chapter 18 port 5 18-1 18. port 5 18.1 overview this lsi includes port 5 (p50 to p57) which is an 8-bit input/output port. 18.1.1 features ? allows selection of n-channe l open drain output or cmos output for each bit in the output mode. ? allows selection of high-impedan ce input or input with a pull-down/pull- up resistor for each bit in the input mode. ? allows selection of interrupt disabled or interrupt enabled for each bit in the input mode. ? the synchronous serial port pins (sin1, sck1, sout1) and the melody 0 (md0) are available as the secondary and tertiary function. 18.1.2 configuration figure 18-1 shows the configuration of port 5. p5d : port 5 data register p5dir : port 5 direction register p5con0 : port 5 control register 0 p5con1 : port 5 control register 1 p5mod0 : port 5 mode register 0 p5mod1 : port 5 mode register 1 p5isel : port 5 interrupt mode register figure 18-1 configuration of port 5 data bus p50 to p57 p5dir p5con0,1 p5mod0 p5mod1 v dd v dd v ss v ss 8 port5 output controller p5d v dd v ss pull-up pull-down controller 8 interrupt controller external 8 interrupt (p5int) sampling clock t16khz p5isel 8 output for sio (sck1, sout1) melody output (md0) input for sio (sin1, sck1) 2 3
ml610q407/ml610q408/ml610q409 user's manual chapter 18 port 5 18-2 18.1.3 list of pins pin name input/output prim ary function secondary function tertiary function p50/exi8/md0/sin1 i/o input/output port, external 8 interrupt melody 0 output ssio1 data input p51/exi8/sck1 i/o input/output port, external 8 interrupt ? ssio1 synchronous clock input/output p52/exi8/sout1 i/o input/output port, external 8 interrupt ? ssio1 data output p53/exi8/md0 i/o input/output port, external 8 interrupt ? ? p54/exi8 i/o input/output port, external 8 interrupt ? ssio1 data input p55/exi8/sin1 i/o input/output port, external 8 interrupt ? ssio1 synchronous clock input/output p56/exi8/sck1 i/o input/output port, external 8 interrupt ? ssio1 data output p57/exi8/sout1 i/o input/output port, external 8 interrupt ? ? 18.2 description of registers 18.2.1 list of registers address name symbol (byte) symbol (word) r/w size initial value 0f228h port 5 data register p5d ? r/w 8 0ffh 0f229h port 5 direction r egister p5dir ? r/w 8 00h 0f22ah port 5 control regist er 0 p5con0 r/w 8/16 00h 0f22bh port 5 control register 1 p5con1 p5con r/w 8 00h 0f22ch port 5 mode register 0 p5mod0 r/w 8/16 00h 0f22dh port 5 mode register 1 p5mod1 p5mod r/w 8 00h 0f22eh port 5 interrupt mode r egister p5isel ? r/w 8 00h
ml610q407/ml610q408/ml610q409 user's manual chapter 18 port 5 18-3 18.2.2 port 5 data register (p5d) address: 0f228h access: r/w access size: 8-bit initial value: 0ffh 7 6 5 4 3 2 1 0 p5d p57d p56d p55d p54d p53d p52d p51d p50d r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 1 1 1 1 1 1 1 1 p5d is a special function register (sfr) to set the value to be output to the port 5 pin or to read the input level of the port 5. in output mode, the value of this register is output to the port 5 pin. the value written to p5d is readable. in input mode, the input level of the port 5 pin is read when p5d is read. output mode or input m ode is selected by using the p ort direction register (p5d ir) described later. [description of bits] ? p57d to p50d (bit 7 to 0) the p57d to p50d bits are used to set the output value of the port 5 pin in output mode and to read the pin level of the port 5 pin in input mode. p57d description 0 output or input leve l of the p57 pin: "l" 1 output or input leve l of the p57 pin: "h" p56d description 0 output or input leve l of the p56 pin: "l" 1 output or input leve l of the p56 pin: "h" p55d description 0 output or input leve l of the p55 pin: "l" 1 output or input leve l of the p55 pin: "h" p54d description 0 output or input leve l of the p54 pin: "l" 1 output or input leve l of the p54 pin: "h" p53d description 0 output or input leve l of the p53 pin: "l" 1 output or input leve l of the p53 pin: "h" p52d description 0 output or input leve l of the p52 pin: "l" 1 output or input leve l of the p52 pin: "h" p51d description 0 output or input leve l of the p51 pin: "l" 1 output or input leve l of the p51 pin: "h" p50d description 0 output or input leve l of the p50 pin: "l" 1 output or input leve l of the p50 pin: "h"
ml610q407/ml610q408/ml610q409 user's manual chapter 18 port 5 18-4 18.2.3 port 5 direction register (p5dir) address: 0f229h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 p5dir p57dir p56dir p55dir p54dir p53dir p52dir p51dir p50dir r/w r/w r/w r/w r/ w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 p5dir is a special function register (sfr) to select the input/output mode of port 5. [description of bits] ? p57dir to p50dir (bit 7 to 0) the p57dir to p50dir pins are used to set the input/output direction of the port 5 pin. p57dir description 0 p57 pin: output (initial value) 1 p57 pin: input p56dir description 0 p56 pin: output (initial value) 1 p56 pin: input p55dir description 0 p55 pin: output (initial value) 1 p55 pin: input p54dir description 0 p54 pin: output (initial value) 1 p54 pin: input p53dir description 0 p53 pin: output (initial value) 1 p53 pin: input p52dir description 0 p52 pin: output (initial value) 1 p52 pin: input p51dir description 0 p51 pin: output (initial value) 1 p51 pin: input p50dir description 0 p50 pin: output (initial value) 1 p50 pin: input
ml610q407/ml610q408/ml610q409 user's manual chapter 18 port 5 18-5 18.2.4 port 5 control registers 0 and 1 (p5con0 and p5con1) address: 0f22ah access: r/w access size: 8/16 bit initial value: 00h 7 6 5 4 3 2 1 0 p5con0 p57c0 p56c0 p55c0 p54c0 p53c0 p52c0 p51c0 p50c0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 address: 0f22bh access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 p5con1 ? ? ? ? ? ? ? p5ud r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 p5con0 and p5con1 are special function registers (sfrs) to select input/output state of the port 5 pin. the input/output state is different between input mode and output mode. input or output is selected by using the p5dir register. [description of bits] ? p57c0 to p50c0 (bit 7 to 0) p57c0 to p50c0 are the bits that select n-channel open drain output or cmos output in the output mode, and high-impedance input or input with a pull-down or pull-up resistor in the input mode. setting of p57 pin when output mode is selected (p57dir bit = "0") when input mode is selected (p57dir bit = "1") p57c0 description 0 n-channel open drain output (initial value) i nput with a pull-down or pull-up resistor 1 cmos output high-impedance input setting of p56 pin when output mode is selected (p56dir bit = "0") when input mode is selected (p56dir bit = "1") p56c0 description 0 n-channel open drain output (initial value) input with a pull-down or pull-up resistor 1 cmos output high-impedance input setting of p55 pin when output mode is selected (p55dir bit = "0") when input mode is selected (p55dir bit = "1") p55c0 description 0 n-channel open drain output (initial value) i nput with a pull-down or pull-up resistor 1 cmos output high-impedance input setting of p54 pin when output mode is selected (p54dir bit = "0") when input mode is selected (p54dir bit = "1") p54c0 description 0 n-channel open drain output (initial value) i nput with a pull-down or pull-up resistor 1 cmos output high-impedance input
ml610q407/ml610q408/ml610q409 user's manual chapter 18 port 5 18-6 setting of p53 pin when output mode is selected (p53dir bit = "0") when input mode is selected (p53dir bit = "1") p53c0 description 0 n-channel open drain output (initial value) i nput with a pull-down or pull-up resistor 1 cmos output high-impedance input setting of p52 pin when output mode is selected (p52dir bit = "0") when input mode is selected (p52dir bit = "1") p52c0 description 0 n-channel open drain output (initial value) i nput with a pull-down or pull-up resistor 1 cmos output high-impedance input setting of p51 pin when output mode is selected (p51dir bit = "0") when input mode is selected (p51dir bit = "1") p51c0 description 0 n-channel open drain output (initial value) i nput with a pull-down or pull-up resistor 1 cmos output high-impedance input setting of p50 pin when output mode is selected (p50dir bit = "0") when input mode is selected (p50dir bit = "1") p50c0 description 0 n-channel open drain output (initial value) i nput with a pull-down or pull-up resistor 1 cmos output high-impedance input ? p5ud (bit 0) p5ud is the bit that selects input with a pull-up resistor or input with a pull-down resistor when the input with a pull-down or pull-up resistor is selected. setting of each port 5 pin when the input with a pull-down or pull-up resistor mode is selected (p5ndir bit = "1", p5nc0 = "0") (n = 0,1,2,3,4,5,6,7) p5ud description 0 input with a pull-up resistor (initial value) 1 input with a pull-down resistor
ml610q407/ml610q408/ml610q409 user's manual chapter 18 port 5 18-7 18.2.5 port 5 mode register 0 and 1 (p5mod0 and p5mod1) address: 0f22ch access: r/w access size: 8/16-bit initial value: 00h 7 6 5 4 3 2 1 0 p5mod0 ? p56md0 p55md0 p54md0 ? p52md0 p51md0 p50md0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 address: 0f22dh access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 p5mod1 ? p56md1 p55md1 p54md1 ? p52md1 p51md1 p50md1 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 p5mod0 and p5mod1 are special function registers (sfrs) to select the primary function or the secondary function of port 5. [description of bits] ? p56md1, p56md0 (bit 6) the p56md1 and p56md0 bit is used to select the primary, secondary, or the tertiary function of the p56 pin. p56md1 p56md0 description 0 0 general-purpose input/out put mode (initial value) 0 1 prohibited 1 0 ssio1 data output 1 1 prohibited ? p55md1,p55md0 (bit 5) the p55md1 and p55md0 bit is used to select the primary, secondary, or the tertiary function of the p55 pin. p55md1 p55md0 description 0 0 general-purpose input/out put mode (initial value) 0 1 prohibited 1 0 ssio1 synchronous clock input/output 1 1 prohibited ? p54md1, p54md0 (bit 0) the p54md1 and p54md0 bit is used to select the primary, secondary, or the tertiary function of the p54 pin. p54md1 p54md0 description 0 0 general-purpose input/out put mode (initial value) 0 1 melody 0 output 1 0 ssio1 data input 1 1 prohibited
ml610q407/ml610q408/ml610q409 user's manual chapter 18 port 5 18-8 ? p52md1, p52md0 (bit 2) the p52md1 and p52md0 bit is used to select the primary, secondary, or the tertiary function of the p52 pin. p52md1 p52md0 description 0 0 general-purpose input/out put mode (initial value) 0 1 prohibited 1 0 ssio1 data output 1 1 prohibited ? p51md1,p51md0 (bit 1) the p51md1 and p51md0 bit is used to select the primary, secondary, or the tertiary function of the p51 pin. p51md1 p51md0 description 0 0 general-purpose input/out put mode (initial value) 0 1 prohibited 1 0 ssio1 synchronous clock input/output 1 1 prohibited ? p50md1, p50md0 (bit 0) the p50md1 and p50md0 bit is used to select the primary, secondary, or the tertiary function of the p50 pin. p50md1 p50md0 description 0 0 general-purpose input/out put mode (initial value) 0 1 melody 0 output 1 0 ssio1 data input 1 1 prohibited note: when the pin is set to "prohibited" and the output mode is selected (by the port 5 control register), the port 5 output pin state is fixed as follows regardless of the data of the port data register p5d: when n-channel open drain output is selected: output pin is fixed to "l" when cmos output is selected: output pin is fixed to "l" when using the p54 pin as sio1 data input, set the p50 pin not to be thertialy function in the p5mod0 and p5mod1 registers.
ml610q407/ml610q408/ml610q409 user's manual chapter 18 port 5 18-9 18.2.6 port 5 interrupt mode register (p5isel) address: 0f22eh access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 p5isel p57is p56is p55is p54is p53is p52is p51is p50is r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 p5isel is a special function register ( sfr) to select the pin used for the port 5 external interrupt (p5int). [description of bits] ? p57is to p50is (bit 7 to 0) p57is to p50is are the bits that se lect to disable or enable the in terrupt of each pin on the port 5. p57is description 0 p57 external interrupt disabled (initial value) 1 p57 external interrupt enabled p56is description 0 p56 external interrupt disabled (initial value) 1 p56 external interrupt enabled p55is description 0 p55 external interrupt disabled (initial value) 1 p55 external interrupt enabled p54is description 0 p54 external interrupt disabled (initial value) 1 p54 external interrupt enabled p53is description 0 p53 external interrupt disabled (initial value) 1 p53 external interrupt enabled p52is description 0 p52 external interrupt disabled (initial value) 1 p52 external interrupt enabled p51is description 0 p51 external interrupt disabled (initial value) 1 p51 external interrupt enabled p50is description 0 p50 external interrupt disabled (initial value) 1 p50 external interrupt enabled
ml610q407/ml610q408/ml610q409 user's manual chapter 18 port 5 18-10 18.3 description of operation 18.3.1 input/output port functions for each pin of port 5, either output or input is selected by setting the port 5 direction re gister (p5dir). in the output mode, set the port 5 control register 0 (p5c on0) to select either n-channel open drain output mode or cmos output mode. in the input mode, set the port 5 control registers 0 and 1 (p5con0 and p5con1) to select any of high-impedance input mode, input mode with a pull-down resistor, or input mode with a pull-up resistor. at the system reset, n-channel open drain output mode is selected as the initial state. in output mode, the "l" or "h" level is out put to each pin of port 5 depending on the value set by the port 5 data register (p5d). in input mode, the input level of each pin of port 5 is read from th e port 5 data register (p5d). 18.3.2 secondary and tertiary functions the port 5 is assigned with the pins for melody 0 (md0) output as the secondary function and the pins for synchronous serial port 1 (sin1, sck1, sout1) as the tertiary function. each of them can be used as the secondary or tertiary function by setting the p57md1 to p50md1 and p57md0 to p50md0 bits of the port mode register 1(p5mod1) and 0 (p5mod0). 18.3.3 external interrupt each of the port 5 pins (p50 to p57) can be used as the external 8 interrupt (p5int). each interrupt is maskable and selectable to be disabled or enabled. for details of interrupts, see chapter 5, ?interrupts?.
ml610q407/ml610q408/ml610q409 user's manual chapter 18 port 5 18-11 18.3.4 interrupt request the maskable external 8 interrupt (p5int) occurs wh en each of the port 5 pins has an interrupt edge. figure 18-2 shows the external 8 interrupt (p5int) generation timing in case p5ud bit of p5con1 register is ?1?. figure 18-3 shows the external 8 interrupt (p5int) generation timing in case p5ud bit of p5con1 register is ?0?. note: - the external 8 interrupt (p5int) is fixed to both-edge interrupt with sampling. in stop mode, since the 16 khz sampling clock stops, no sampling is performed. - depending on the p5n pin state, the external 8 interrupt request flag (irq2's bit 3) may be set to "1" when the p5isel setting is changed. therefore, ch ange the p5isel setting when the master interrupt enable (mie) flag is "0", then reset the external 8 interrupt request flag to "0" by software before setting the mie to "1". for interrupts, see chapter 5, "interrupts." with sampling, both-edge interrupt figure 18-2 external 8 interrupt generation timing (p5ud = 1) sysclk p50 pin p5int interrupt request qp5 t16khz p51 pin p52 pin p53 pin p54 pin p55 pin p56 pin p57 pin
ml610q407/ml610q408/ml610q409 user's manual chapter 18 port 5 18-12 with sampling, both-edge interrupt figure 18-3 external 8 interrupt generation timing (p5ud = 0) sysclk p50 pin p5int interrupt request qp5 t16khz p51pin p52 pin p53 pin p54 pin p55 pin p56 pin p57 pin
chapter 19 port 6
ml610q407/ml610q408/ml610q409 user's manual chapter 19 port 6 19-1 19. port 6 19.1 general description ml610q407 includes port 6 (p60 to p67) which is an 8-bit input/output port. ml610q408 includes port 6 (p60 to p63) which is a 4-bit input/output port. ml610q409 this function is not included. 19.1.1 features ? allows selection of n-channel open dr ain output or cmos output for each bit. 19.1.2 configuration figure 19-1 shows the configuration of port 6. p6d : port 6 data register p6con0 : port 6 control register 0 figure 19-1 configuration of port 6 19.1.3 list of pins pin name output function p60 o output port p61 o output port p62 o output port p63 o output port p64 o output port p65 o output port p66 o output port p67 o output port data bus p60 to p67 p6con0, v dd v dd v ss v ss 8 port6 output controller p6d
ml610q407/ml610q408/ml610q409 user's manual chapter 19 port 6 19-2 19.2 description of registers 19.2.1 list of registers address name symbol (byte) symbol (word) r/w size initial value 0f230h port 6 data register p6d ? r/w 8 0ffh (*1) 00fh (*2) 0f232h port 6 control regist er 0 p6con0 ? r/w 8 00h (*1) initial value for ml610407, (*2) initial value for ml610q408
ml610q407/ml610q408/ml610q409 user's manual chapter 19 port 6 19-3 19.2.2 port 6 data register (p6d) address: 0f230h access: r/w access size: 8-bit initial value: 0ffh 7 6 5 4 3 2 1 0 p6d p67d p66d p65d p64d p63d p62d p61d p60d r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 1 1 1 1 1 1 1 1 p6d is a special function register (sfr) to set the output value of the port 6 pins. the value of this register is output to port 6. the value written to p6d is readable. for ml610q408, p67d to p64d always returns the value ?0?. ml610q409 does not have this register. [description of bits] ? p67d to p60d (bit 7 to 0) the p67d to p60d bits are used to set the output value of the port 6 pins. p67d description 0 output level of the p67 pin: "l" 1 output level of the p67 pin: "h" p66d description 0 output level of the p66 pin: "l" 1 output level of the p66 pin: "h" p65d description 0 output level of the p65 pin: "l" 1 output level of the p65 pin: "h" p64d description 0 output level of the p64 pin: "l" 1 output level of the p64 pin: "h" p63d description 0 output level of the p63 pin: "l" 1 output level of the p63 pin: "h" p62d description 0 output level of the p62 pin: "l" 1 output level of the p62 pin: "h" p61d description 0 output level of the p61 pin: "l" 1 output level of the p61 pin: "h" p60d description 0 output level of the p60 pin: "l" 1 output level of the p60 pin: "h"
ml610q407/ml610q408/ml610q409 user's manual chapter 19 port 6 19-4 19.2.3 port 6 control register 0 (p6con0) address: 0f232h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 p6con0 p67c0 p66c0 p65c0 p64c0 p63c0 p62c0 p61c0 p60c0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 p6con0 is a special function registers (sfr) to select input/output state of the port 6 pin. for ml610q408, p67c0 to p64c0 always returns the value ?0?. ml610q409 does not have this register. [description of bits] ? p67c0 to p60c0 (bit 7 to 0) p67c0 to p60c0 are the bits that select either n-channel open drain output or cmos output. p67c0 description 0 n-channel open drain output (initial value) 1 cmos output p66c0 description 0 n-channel open drain output (initial value) 1 cmos output p65c0 description 0 n-channel open drain output (initial value) 1 cmos output p64c0 description 0 n-channel open drain output (initial value) 1 cmos output p63c0 description 0 n-channel open drain output (initial value) 1 cmos output p62c0 description 0 n-channel open drain output (initial value) 1 cmos output p61c0 description 0 n-channel open drain output (initial value) 1 cmos output p60c0 description 0 n-channel open drain output (initial value) 1 cmos output
ml610q407/ml610q408/ml610q409 user's manual chapter 19 port 6 19-5 19.3 description of operation 19.3.1 output port function for each of the port 6 pins, n-channel ope n drain output mode or cmos output mode can be sel ected by setting the port 6 control register 0 (p6con0). at the system reset, n-channel open drain output mode is selected as the initial state. depending on the value set in the port 6 data register (p6d), a "l" level or "h" le vel signal is output to each pin of port 6.
chapter 20 melody driver
ml610q407/ml610q408/ml610q409 user's manual chapter 20 melody driver 20-1 20. melody driver 20.1 overview this lsi includes one channel of the melody driver. to use the melody driver, the secondary function of port 2 or port 5 should be set. for the secondary function of port 2, see chapter 15, "port 2". for the secondary function of port 5, see chapter 18, "port 5".for the clock to be used in this block, see chapter 6, "clock generation circuit". 20.1.1 features ? in melody output mode, 29 scales (melody audi o frequency: 508hz to 32.768khz), 63 tone lengths, and 15 tempos) are available. ? in buzzer output mode, 4 output modes, 8 frequencies, and 15 duties can be set. 20.1.2 configuration figure 20-1 shows the configuration of the melody driver. md0con : melody 0 control register md0tmp : melody 0 tempo code register md0ton : melody 0 scale code register md0len : melody 0 tone length code register figure 20-1 configuration of melody driver 20.1.3 list of pins pin name i/o function p22/md0 o melody 0 signal output pin used as the secondary f unction of the p22 pin. p50/md0 o melody 0 signal output pin used for the secondary f unction of the p50 pin. scale codes md0ton data bus tone length codes md0len scale buffer tone length buffer scale generation circuit/ buzzer output circuit tempo codes md0tmp tone length generation circuit/ duty selection circuit control circuit md0con tempo generation circuit/ buzzer mode selection circuit p22/md0 p50/md0 md0int melody interrupt lsclk x 2
ml610q407/ml610q408/ml610q409 user's manual chapter 20 melody driver 20-2 20.2 description of registers 20.2.1 list of registers address name symbol (byte) symbol (word) r/w size initial value 0f2c0h melody 0 control register md0con ? r/w 8 00h 0f2c1h melody 0 tempo code register md0tmp ? r/w 8 00h 0f2c2h melody 0 scale code register md0ton r/w 8/16 00h 0f2c3h melody 0 tone length code register md0len md0tl r/w 8 00h
ml610q407/ml610q408/ml610q409 user's manual chapter 20 melody driver 20-3 20.2.2 melody 0 control register (md0con) address: 0f2c0h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 md0con ? ? ? ? ? ? bzmd m0run r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 md0con is a special function register (sfr) to control the melody and the buzzer. [description of bits] ? bzmd (bit 1) the bzmd bit is used to select melody mode or buzzer mode. bzmd description 0 melody mode (initial value) 1 buzzer mode ? m0run (bit 0) the m0run bit is used to control start/stop of the md0 output. m0run description 0 stops md0 output. (initial value) 1 starts md0 output. note: for melody output, use the low-speed double clock (lsclk x 2). enable the low-speed double clock by setting bit 2 (enmlt) of frequency cont rol register 1 (fcon1) to ?1? and then start melody output by setting m0run to ?1?.
ml610q407/ml610q408/ml610q409 user's manual chapter 20 melody driver 20-4 20.2.3 melody 0 tempo code register (md0tmp) address: 0f2c1h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 md0tmp ? ? ? ? m0tm3 m0tm2 m0tm1 m0tm0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 md0tmp is a special function register (sfr) to set the tempo code of a melody when melody mode is selected and the output mode of a buzzer sound waveform when buzzer mode is selected. [description of bits] ? m0tm3, m0tm2, m0tm1, m0tm0 (bits 3-0) when melody mode is selected (bzmd bit = ? 0 ? ) m0tm3 m0tm2 m0tm1 m0tm0 description 0 0 0 0 ? = 480 (initial value) 0 0 0 1 ? =480 0 0 1 0 ? =320 0 0 1 1 ? =240 0 1 0 0 ? =192 0 1 0 1 ? =160 0 1 1 0 ? ? 137 0 1 1 1 ? =120 1 0 0 0 ? ? 107 1 0 0 1 ? =96 1 0 1 0 ? ? 87 1 0 1 1 ? =80 1 1 0 0 ? ? 74 1 1 0 1 ? ? 69 1 1 1 0 ? =64 1 1 1 1 ? =60 when buzzer mode is selected (bzmd bit = ?1?) m0tm3 m0tm2 m0tm1 m0tm0 description * * 0 0 intermittent sound 1 output (initial value) * * 0 1 intermittent sound 2 output * * 1 0 single sound output * * 1 1 continuous sound output
ml610q407/ml610q408/ml610q409 user's manual chapter 20 melody driver 20-5 20.2.4 melody 0 scale code register (md0ton) address: 0f2c2h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 md0ton ? m0tn6 m0tn5 m0tn4 m0tn3 m0tn2 m0tn1 m0tn0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 md0ton is a special function register (sfr ) to set the scale code of a melody when melody mode is selected and a buzzer output frequency when buzzer mode is selected. [description of bits] ? m0tn6, m0tn5, m0tn4, m0tn3, m0tn2, m0tn1, m0tn0 (bits 6-0) when melody mode is selected (bzmd bit = ?0?) description m0tn6 0 sets the corresponding scale code. for scale codes, see section 20.3.4, "scale codes". when buzzer mode is selected (bzmd bit = ?1?) m0tn6 3 m0tn2 m0tn1 m0tn0 description * 0 0 0 4.096 khz (initial value) * 0 0 1 2.048khz * 0 1 0 1.365khz * 0 1 1 1.024khz * 1 0 0 819hz * 1 0 1 683hz * 1 1 0 585hz * 1 1 1 512hz note: in buzzer mode, the m0 tn6 to m0tn3 bits are not used (don't care).
ml610q407/ml610q408/ml610q409 user's manual chapter 20 melody driver 20-6 20.2.5 melody 0 tone length code register (md0len) address: 0f2c3h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 md0len ? ? m0ln5 m0ln4 m0ln3 m0ln2 m0ln1 m0ln0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 md0len is a special function register (sfr) to set the tone length code of a melody when melody mode is selected and buzzer output duty when buzzer mode is selected. [description of bits] ? m0ln5, m0ln4, m0ln3, m0ln2, m0ln1, m0ln0 (bits 5-0) when melody mode is selected (bzmd bit = ?0?) description m0ln5 0 sets the corresponding tone length code. for tone length codes, see section 20.3.3, "tone length codes". when buzzer mode is selected (bzmd bit = ?1?) m0ln5 4 m0ln3 m0ln2 m0ln1 m0ln0 description * 0 0 0 0 1/16 duty (initial value) * 0 0 0 1 1/16duty * 0 0 1 0 2/16duty * 0 0 1 1 3/16duty * 0 1 0 0 4/16duty * 0 1 0 1 5/16duty * 0 1 1 0 6/16duty * 0 1 1 1 7/16duty * 1 0 0 0 8/16duty * 1 0 0 1 9/16duty * 1 0 1 0 10/16duty * 1 0 1 1 11/16duty * 1 1 0 0 12/16duty * 1 1 0 1 13/16duty * 1 1 1 0 14/16duty * 1 1 1 1 15/16duty note: in buzzer mode, the m0 ln5 to m0ln4 bits are not used (don't care).
ml610q407/ml610q408/ml610q409 user's manual chapter 20 melody driver 20-7 20.3 description of operation 20.3.1 operation of melody output melody is output in the following procedure. (1) select melody mode by setting the bzmd bit of the melody 0 control register (md0con) to ?0?. (2) set a melody tempo in the melody 0 tempo code register (md0tmp). (3) set a tone length code in the melody 0 tone length code register (md0len). (4) set a scale code in the melody 0 scale code register (md0ton). (5) set bit 2 (enmlt) of the frequency control register 1(fcon1) to ?1? to enable the low-speed double clock. (6) when the m0run bit of the melody 0 control register (md0c on) is set to ?1?, the tone length code and scale code are transferred to the tone length buffer and scale buffer and melody output is started from the md0 pin. at the same time, a melody 0 interrupt (md0int) is requested. when an interrupt occurs and program is passed to the interrupt routine, the interrupt request flag is cleared. the melody 0 signal output pin (md0) is assigned as the sec ondary function of port 2 or port 5. for the secondary function of port 2 or port 5, see chapter 15, "port 2" or chapter 18, "port 5". in the software processing after melody 0 interrupt, the tone length code and the scale code of the note that are output next are set to md0len and md0ton, resp ectively. when there is no next note to be output, rest data ?00h? is set in md0ton, the m0run bit is set to ?0? by the software processing after the next melody 0 interrupt, and melody output is terminated. by setting the m0run bit to ?0?, melody can be terminated forcibly during melody output. figure 20-2 shows the operation waveform of the melody driver. figure 20-2 operation waveform of melody driver m0run md0int xx 1st sound 2nd sound xx 1st sound waveform 2nd sound 3rd sound 3rd sound final rest data final sound rest data md0len md0ton tone length/scale buffer melody output waveform md0* 2nd sound waveform 3rd sound waveform 1st sound final sound waveform
ml610q407/ml610q408/ml610q409 user's manual chapter 20 melody driver 20-8 20.3.2 tempo codes a tempo code is set in the melody 0 tempo code register (md0tem). table 20-1 shows the correspondence between tempos ( number of counts for one minute) and tempo codes. the tempo when all the bits are set to "0" is equal to the shortest tone length (the tempo when the only m0tp0 bit is set to "1"). table 20-1 correspondence between tempos and tempo codes tempo code (md0tmp) tempo m0tp3 m0tp2 m0tp1 m0tp0 m0tp3 0 = 480 0 0 0 0 0h = 480 0 0 0 1 1h = 320 0 0 1 0 2h = 240 0 0 1 1 3h = 192 0 1 0 0 4h = 160 0 1 0 1 5h ? 137 0 1 1 0 6h = 120 0 1 1 1 7h ? 107 1 0 0 0 8h = 96 1 0 0 1 9h ? 87 1 0 1 0 ah = 80 1 0 1 1 bh ? 74 1 1 0 0 ch ? 69 1 1 0 1 dh = 64 1 1 1 0 eh = 60 1 1 1 1 fh
ml610q407/ml610q408/ml610q409 user's manual chapter 20 melody driver 20-9 20.3.3 tone length codes a tone length code is set in the melody 0 tone length code register (md0len). table 20-2 shows the correspondence between tone lengths and tone length codes. the tone length when all the bits are set to "0" is equal to the shortest tone length (the tone length when the only m0ln0 bit is set to "1"). table 20-2 correspondence between tone lengths and tone length codes tone length code (md0len) tone length m0ln5 m0ln4 m0ln3 m0ln2 m0ln1 m0ln1 m0ln5 0 1 1 1 1 1 1 3fh 1 0 1 1 1 1 2fh 0 1 1 1 1 1 1fh 0 1 0 1 1 1 17h 0 0 1 1 1 1 0fh 0 0 1 0 1 1 0bh 0 0 0 1 1 1 07h 0 0 0 1 0 1 05h 0 0 0 0 1 1 03h 0 0 0 0 1 0 02h 0 0 0 0 0 1 01h the tone length set by a tone length code and a te mpo code is expressed by the following equation. tone length = 1.953125 x ( tp + 1 ) x ( ln + 1 ) ms where tp is an integer of 1 to 15, and ln is an integer of 1 to 63. the bit correspondence between tp and tempo c odes is expressed by the following equation. tp = 2 3 m0tp3 + 2 2 m0tp2 + 2 1 m0tp1 + 2 0 m0tp0 the bit correspondence between ln and tone length codes is expressed by the following equation. ln = 2 5 m0ln5 + 2 4 m0ln4 + 2 3 m0ln3 + 2 2 m0ln2 + 2 1 m0ln1 + 2 0 m0ln0
ml610q407/ml610q408/ml610q409 user's manual chapter 20 melody driver 20-10 20.3.4 scale codes a scale code is set in the melody 0 scale code register (md0ton). in the melody driver, a frequency that can be output is expressed by the following equation. 65536 ( tn + 1 ) hz (where tn is an integer of 4 to 127.) the bit correspondence between tn and scale c odes is expressed by the following equation. tn = 2 6 m0tn6 + 2 5 m0tn5 + 2 4 m0tn4 + 2 3 m0tn3 + 2 2 m0tn2 + 2 1 m0tn1 + 2 0 m0tn0 table 20-3 shows the correspondence between scales and scale codes. when the m0tn6 to m0tn2 bits are set to "0", scale becomes a rest. the rest length is set by the tone length code (md0len). table 20-3 correspondence between scales and scale codes scale code (md0ton) scale frequency (hz) m0tn6 m0tn5 m0tn4 m0tn3 m0tn2 m0tn1 m0tn0 m0tn6 0 c 1 529 1 1 1 1 0 1 1 7bh cis 1 560 1 1 1 0 1 0 0 74h d 1 590 1 1 0 1 1 1 0 6eh dis 1 624 1 1 0 1 0 0 0 68h e 1 662 1 1 0 0 0 1 0 62h f 1 705 1 0 1 1 1 0 0 5ch fis 1 745 1 0 1 0 1 1 1 57h g 1 790 1 0 1 0 0 1 0 52h gis 1 840 1 0 0 1 1 0 1 4dh a 1 886 1 0 0 1 0 0 1 49h ais 1 936 1 0 0 0 1 0 1 45h b 1 993 1 0 0 0 0 0 1 41h c 2 1057 0 1 1 1 1 0 1 3dh cis 2 1111 0 1 1 1 0 1 0 3ah d 2 1192 0 1 1 0 1 1 0 36h dis 2 1260 0 1 1 0 0 1 1 33h e 2 1338 0 1 1 0 0 0 0 30h f 2 1394 0 1 0 1 1 1 0 2eh fis 2 1490 0 1 0 1 0 1 1 2bh g 2 1560 0 1 0 1 0 0 1 29h gis 2 1680 0 1 0 0 1 1 0 26h a 2 1771 0 1 0 0 1 0 0 24h ais 2 1872 0 1 0 0 0 1 0 22h b 2 1986 0 1 0 0 0 0 0 20h c 3 2114 0 0 1 1 1 1 0 1eh d 3 2341 0 0 1 1 0 1 1 1bh dis 3 2521 0 0 1 1 0 0 1 19h e 3 2621 0 0 1 1 0 0 0 18h fis 3 2979 0 0 1 0 1 0 1 15h
ml610q407/ml610q408/ml610q409 user's manual chapter 20 melody driver 20-11 20.3.5 example of using melody circuit figure 20-3 shows an example of a melody notation, and table 20-4 shows note codes of melody examples. 1 figure 20-3 example of melody notation table 20-4 note codes of melody examples note code md0len md0ton note 5 4 3 2 1 0 6 5 4 3 2 1 0 hexade cimal g 2 1 0 1 1 1 1 0 1 0 1 0 0 0 2f28h d 2 0 0 1 1 1 1 0 1 1 0 1 0 1 0f35h g 2 0 0 1 1 1 1 0 1 0 1 0 0 0 0f28h ? 0 0 0 1 1 1 0 0 0 0 0 0 0 0700h d 2 0 0 0 1 1 1 0 1 1 0 1 0 1 0735h g 2 0 0 1 1 1 1 0 1 0 1 0 0 0 0f28h ? 0 0 0 1 1 1 0 0 0 0 0 0 0 0700h a 2 0 0 0 1 1 1 0 1 0 0 0 1 1 0723h b 2 1 1 1 1 1 1 0 0 1 1 1 1 1 3f1fh g 2 1 1 1 1 1 1 0 1 0 1 0 0 0 3f28h
ml610q407/ml610q408/ml610q409 user's manual chapter 20 melody driver 20-12 20.3.6 operations of buzzer output a buzzer sound is output in the following procedure. (1) select a buzzer mode by setting the bzmd bit of the melody 0 control regi ster (md0con) to ?1?. (2) select a buzzer output m ode using the melody 0 tem po code register (md0tmp). (3) select a duty of the high level widt h of the buzzer output waveform using th e melody 0 tone le ngth code register (md0len). (4) set the buzzer output frequency in the me lody 0 scale code register (md0ton). (5)set bit 2 (enmlt) of the frequency control register 1(fcon1) to ?1? to enable the low-speed double clock. (6) when the m0run bit of the melody 0 control register (md0con) is set to ?1?, the waveform equivalent to the buzzer sound that is set from the md0 pin is output. figure 20-4 shows the output wavefo rm of each buzzer output mode. figure 20-4 output waveform of each buzzer output mode md0con.m0run t8hz buzzer output waveform md0* (1/4) intermittent sound 1 output waveform md0con.m0run t8hz buzzer output waveform md0* (2/4) intermittent sound 2 output waveform md0con.m0run t8hz buzzer output waveform md0* (3/4) single sound output waveform t1hz md0con.m0run buzzer output waveform md0* (4/4) continuous sound output waveform
ml610q407/ml610q408/ml610q409 user's manual chapter 20 melody driver 20-13 20.4 specifying port registers to enable the melody or buzzer function, the applicable bit of each related port regi ster needs to be set. see chapter 15, "port 2" for detail about the port registers. 20.4.1 functioning p22 pin (md0: output) as the melody or buzzer output set the p22md bit (p2mod register bit 0) to ?1? for selecting the melody or bu zzer output as the s econdary function of the p22. register name p2mod register (address: 0f214h) bit 7 6 5 4 3 2 1 0 bit name - - - - - p22md p21md p20md setting value - - - - - 1 * * set the p22c1 bit (p2con1 register bit 0) to ?1? and the p22c0 bit (p2con0 register bit 0) to ?1? for selecting the p22 pin state mode to cmos output. register name p2con1 register (address: 0f213h) bit 7 6 5 4 3 2 1 0 bit name - - - - - p22c1 p21c1 p20c1 setting value - - - - - 1 * * register name p2con0 register (address: 0f212h) bit 7 6 5 4 3 2 1 0 bit name - - - - - p22c0 p21c0 p20c0 setting value - - - - - 1 * * data of p22d bit (bit0 of p2d registe r) does not affect to the melody or buzzer function, so don?t care the data for the function. register name p2d register (address: 0f210h) bit 7 6 5 4 3 2 1 0 bit name - - - - - p22d p21d p20d setting value - - - - - ** * * - : bit that does not exist * : bit not related to the melody function ** : don?t care note: z p2 (port 2) is an output-only pin and does not have the re gister to select the data direction(input or output). z the p22 pin output characteristics are vol1 and voh1 (des cribed in appendix c, "e lectrical characteristics") when the p22md bit is "1" (melody/buzzer is selected as the secondary function), and vol2 and voh2 when the bit is "0".
ml610q407/ml610q408/ml610q409 user's manual chapter 20 melody driver 20-14 20.4.2 functioning p50 pin (md0: output) as the melody or buzzer output set the p50md1 bit (p5mod1 register bit 0) to ?0? and the p50md0 bit (p5mod0 register bit 0) to ?1? for selecting the melody or buzzer output as th e secondary function of the p50. register name p5mod1 register (address: 0f22dh) bit 7 6 5 4 3 2 1 0 bit name - p56md1 p55md1 p54md1 - p52md1 p51md1 p50md1 setting value - * * * * * * 1 register name p5mod0 register (address: 0f22ch) bit 7 6 5 4 3 2 1 0 bit name - p56md0 p55md0 p54md0 - p52md0 p51md0 p50md0 setting value - * * * * * * 1 set the the p50c0 bit (p5con0 register bit 0) to ?1? for selecting the p50 pin state mode to cmos output. set the p50dir bit (p5dir register bit 0) to ?0? for selecting the p50 as an output pin. the p5ud bit (p5con1 register bit 0) data can either be "0" or "1". register name p5con1 register (address: 0f22bh) bit 7 6 5 4 3 2 1 0 bit name - - - - - - - p5ud setting value - - - - - - - * register name p5con0 register (address: 0f22ah) bit 7 6 5 4 3 2 1 0 bit name p57c0 p56c0 p55c0 p54c0 p53c0 p52c0 p51c0 p50c0 setting value * * * * * * * 1 register name p5dir register (address: 0f229h) bit 7 6 5 4 3 2 1 0 bit name p57dir p56dir p55dir p54dir p53dir p52dir p51dir p50dir setting value * * * * * * * 0
ml610q407/ml610q408/ml610q409 user's manual chapter 20 melody driver 20-15 the p50d bit (p5d register bit 0) data can either be "0" or "1". register name p5d register (address: 0f228h) bit 7 6 5 4 3 2 1 0 bit name p57d p56d p55d p54d p53d p52d p51d p50d setting value - - - - * * * ** - : bit that does not exist * : bit not related to the melody function ** : don?t care
chapter 2 rc oscillation type a/d converter
ml610q407/ml610q408/ml610q409 user's manual chapter 21 rc oscillation type a/d converter 21-1 21. rc oscillation type a/d converter 21.1 overview this lsi has a built-in 2-channel rc os cillation type a/d converter (rc-adc). the rc-adc converts resistance values or capacitance values to digital values by counting the oscillator clock whose frequency changes according to the resistor or capacitor connected to the rc oscillato r circuits. by using a thermistor or humidity sensor as a resistor, a thermometer or hygrometer can be formed. in addition, a different sensor for each of the two channels of rc-adc?s rc osc illator circuit can be used to broaden rc-adc applications; for example, the converter can be used for expansion of measurement range or measurement at two points. for input clocks, see chapter 6, ?clock generation circuit?. 21.1.1 features ? 2-channel system by time division 21.1.2 configuration the rc-adc consists of two rc oscillator circuits to form two channels, counter a (radca0 and radca1) and counter b (radcb0 and radcb1) as 16-bit binary counters, and an rc-adc control circuit (radcon, radmod). figure 21-1 shows the configuration of the rc-adc. radmod : rc-adc mode register radcon : rc-adc control register radca0 1 : rc-adc counter a register radcb0 1 : rc-adc counter b register figure 21-1 configuration of rc-adc rc oscillation (rcosc0) data bus p30/in0 lsclk rc-adc control circuit (radcon) (radmod) interrupt control radint p31/cs0 p32/rs0 p33/rt0 p34/rct0 p44/in1 p45/cs1 p46/rs1 p47/rt1 rc oscillation (rcosc1) 16bits binary counter p35/rcm 16bits binary counter counter a (radca0 and radca1 ) counter b (radcb0 and radcb1) rcclk ovfa ovfb clock control circuit lsclk2 hsclk bsclk
ml610q407/ml610q408/ml610q409 user's manual chapter 21 rc oscillation type a/d converter 21-2 21.1.3 list of pins pin name i/o function p30/in0 i channel 0 oscillation input pin. used for the secondary f unction of the p30 pin. p31/cs0 o channel 0 reference capacitor connection pin. used for the secondary f unction of the p31 pin. p32/rs0 o channel 0 reference resistor connection pin. used for the secondary f unction of the p32 pin. p33/rt0 o pin for connection with a resistive sensor for measurement on channel 0. used for the secondary f unction of the p33 pin. p34/rct0 o pin for connection with a resi stive/capacitive sensor for measurement on channel 0. used for the secondary f unction of the p34 pin. p35/rcm o rc oscillation monitor pin. used for the secondary f unction of the p35 pin. p44/in1 i channel 1 oscillation input pin. used for the secondary f unction of the p44 pin. p45/cs1 o channel 1 reference capacitor connection pin. used for the secondary f unction of the p45 pin. p46/rs1 o channel 1 reference resistor connection pin. used for the secondary f unction of the p46 pin. p47/rt1 o pin for connection with a resistive sensor for measurement on channel 1. used for the secondary f unction of the p47 pin.
ml610q407/ml610q408/ml610q409 user's manual chapter 21 rc oscillation type a/d converter 21-3 21.2 description of registers 21.2.1 list of registers address name symbol(byte) symbol (word) r/w size initial value 0f300h rc-adc counter a register 0 radca0 ? r/w 8 00h 0f301h rc-adc counter a register 1 radca1 ? r/w 8 00h 0f304h rc-adc counter b register 0 radcb0 ? r/w 8 00h 0f305h rc-adc counter b register 1 radcb1 ? r/w 8 00h 0f308h rc-adc mode register radmod ? r/w 8 00h 0f309h rc-adc control register radcon ? r/w 8 00h
ml610q407/ml610q408/ml610q409 user's manual chapter 21 rc oscillation type a/d converter 21-4 21.2.2 rc-adc counter a registers (radca0?1) address: 0f300h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 radca0 raa7 raa6 raa5 raa4 raa3 raa2 raa1 raa0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 address: 0f301h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 radca1 raa15 raa14 raa13 raa12 raa11 raa10 raa9 raa8 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 radca0 and radca1 are special function registers (sfrs) for reading from and writing to the counter a of the rc-adc. radca0 and radca1 are 16-bit binary counters. note: after writing data into the rc-adc counter a register, be sure to read it to check that the data has been written correctly. when a/d conversion starts after data is written, the va lue that has been written is read during a/d conversion (rarun = 1). when a/d conversion terminates (rarun = 0), the count value is read.
ml610q407/ml610q408/ml610q409 user's manual chapter 21 rc oscillation type a/d converter 21-5 21.2.3 rc-adc counter b registers (radcb0?1) address: 0f304h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 radcb0 rab7 rab6 rab5 rab4 rab3 rab2 rab1 rab0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 address: 0f305h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 radcb1 rab15 rab14 rab13 rab12 rab11 rab10 rab9 rab8 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 radcb0 and radcb1 are special function registers (sfrs) for reading from and writing to the counter b of the rc-adc. radcb0 and radcb1 are 16-bit binary counters. note: after writing data into the rc-adc counter b register, be sure to read it to check that the data has been written correctly. when a/d conversion starts after data is written, the va lue that has been written is read during a/d conversion (rarun = 1). when a/d conversion terminates (rarun = 0), the count value is read.
ml610q407/ml610q408/ml610q409 user's manual chapter 21 rc oscillation type a/d converter 21-6 21.2.4 rc-adc mode register (radmod) address: 0f308h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 radmod rack2 rack1 rack0 radi om3 om2 om1 om0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 radmod is a special function register (sfr) used to select the a/d conversion mode of the rc-adc. [description of bits] ? om3-0 (bits 3 to 0) the om3?0 bits are used to select an osc illation mode for the rc oscillator circuits. om3 om2 om1 om0 description 0 0 0 0 in0 pin external clock input mode (initial value) 0 0 0 1 rs0-cs0 oscillation mode 0 0 1 0 rt0?cs0 oscillation mode 0 0 1 1 rt 0-1 ?cs0 oscillation mode 0 1 0 0 rs0?ct0 oscillation mode 0 1 0 1 rs1?cs1 oscillation mode 0 1 1 0 rt1?cs1 oscillation mode 0 1 1 1 in1 pin external clock input mode 1 * * * prohibited ? radi (bit 4) the radi bit is used to choose whether to generate the rc-adc interrupt request signal (radint) by an overflow at counter a or counter b. radi description 0 generates an interrupt request by c ounter a overflow (initial value). 1 generates an interrupt reques t by counter b overflow. ? rack2-0 (bits 7 to 5) the rack2 to rack0 bits are used to select the base clock of counter a (bsclk). rack2 rack1 rack0 description 0 0 0 lsclk (initial value) 0 0 1 lsclk2 0 1 0 hsclk 0 1 1 1/2hsclk 1 0 0 1/4hsclk 1 0 1 1/8hsclk 1 1 * setting prohibited (no clock is supplied) note: when specifying lsclk x 2 for the base clock, enable the operation of the low-speed double clock by setting bit 2 (enmlt) of the frequency control register 1 (fcon1) to ?1?.
ml610q407/ml610q408/ml610q409 user's manual chapter 21 rc oscillation type a/d converter 21-7 21.2.5 rc-adc control register (radcon) address: 0f309h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 radcon ? ? ? ? ? ? ? rarun r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 radcon is a special function register (sfr) used to control a/d conversion operation of the rc-adc. [description of bits] ? rarun (bit 0) the rarun bit is used to start or stop a/d conversion of the rc-adc. when rarun is set to ?1?, a/d conversion starts and when set to ?0?, a/d convers ion stops. if counter a or counter b overflows with rarun set to ?1?, the bit is automatically reset to ?0?. rarun is set to ?0? at system reset. rarun description 0 stops a/d conversion (initial value). 1 starts a/d conversion.
ml610q407/ml610q408/ml610q409 user's manual chapter 21 rc oscillation type a/d converter 21-8 21.3 description of operation counter a (radca0 and radca1) is a 16-bit binary counter for counting the base clock (bsclk), which is used as the standard of time. counter a can count up to 0ffffh. counter b (radcb0 to radcb1) is a 16-bit binary counter for counting th e oscillator clock (rcclk) of the rc oscillator circuits. counter b can count up to 0ffffh. counters a and b are provided with overflow flags (ovfa a nd ovfb, respectively). each overflow output results in generation of an rc-adc interrupt request signal (radint ). use the radi bit of the rc-ac mode register (radmod) to select whether to generate an overflow inte rrupt by an overflow on count er a or counter b: setting radi to ?0? specifies counter a overflow and setting it to ?1 ? specifies counter b overflow. the rarun bit of the rc-ad control register (radcon) is used to start or stop rc-adc conversion operation. when rarun is set to ?0?, the oscillato r circuits stop, so that counting will not be performed. when rarun is set to ?1?, rc oscillation starts, when the rc oscillator clock ( rcclk) and the base clock (b sclk) start counting through counter b and counter a. the rc oscillation section has a total of eight types of oscillation modes based on the two oscillator circuits of rcosc0 and rcosc1, and mode selection is made by the rc-adc mode register (radmod). p30?34, p44?47, and p35 must be configured as their s econdary function input or output when using 1) the rc oscillator circuit rcosc0, 2) the rc oscillator circuit rcosc1, and 3) the rc monitor pin (rcm) that outputs rc oscillation waveforms, respectively. for the rc oscillator circuit configuration, see "21.1.2 configuration." for the secondary functions of port 3, see chapter 16, ?port 3.? for the secondary functions of port 4, see chapter 17, ?port 4.? 21.3.1 rc oscillator circuits rc-adc performs a/d conversi on by converting the oscilla tion frequency ratio between a reference resistor (or capacitor) and a resistive sensor (or capacitive sensor) such as a thermistor to digital data. by making rc oscillation occur both on the reference side and on the sensor side with the reference capacitor the error factor that the rs oscillator circuit its elf is eliminated, thereby making it possibl e to perform the a/d conversion of the characteristics of the sensor itself. also, by calculating the ratio between the oscillation frequency on the reference side and that on the sensor side and then calculating the correlation between the calculated ratio and temper atures that the sensor char acteristics have in advance, a temperature can be obtained based on that calculated ratio. table 21-1 lists the eight types of oscillation modes, one of which is selected by the rc-adc mode register (radmod) om3?0 bits. table 21-1 oscillation modes from which selection is made by om3?0 bits radmod rcosc0 output pin rcosc1 output pin mode no. om3 om2 om1 om0 rs0 rt0 crt0 cs0 rs1 rt1 cs1 mode 0 0 0 0 0 z z z z z z z in0 external clock input mode 1 0 0 0 1 1/0 z z 0/1 z z z rs0?cs0 oscillation 2 0 0 1 0 z 1/0 z 0/1 z z z rt0?cs0 oscillation 3 0 0 1 1 z z 1/0 0/1 z z z rt 0-1 ?cs0 oscillation 4 0 1 0 0 1/0 z 0/1 z z z z rs0?ct0 oscillation rcosc0 oscillation mode 5 0 1 0 1 z z z z 1/0 z 0/1 rs1?cs1 oscillation 6 0 1 1 0 z z z z z 1/0 0/1 rt1?cs1 oscillation rcosc1 oscillation mode 7 0 1 1 1 z z z z z z z in1 external clock input mode 8 1 * * * z z z z z z z (prohibited) note) * : indicates arbitrary. z : indicates high-impedance output. 1/0, 0/1 : indicates active output. (prohibited) : the oscillator clock is not supplied even by setting the rarun bit to ? 1 ? or by starting a/d conversion.
ml610q407/ml610q408/ml610q409 user's manual chapter 21 rc oscillation type a/d converter 21-9 in table 21-1, mode no.0 and mode no.7 are modes where external clocks to be input to the in0 or in1 pin are used for measurement with the rc os cillator circuit stopped. as shown in table 21-1, the two oscillator circuits, rcosc 0 and rcosc1, are so specified that they cannot operate concurrently in order to prevent interference in oscillation from occurring when they oscillate concurrently. the relationship between an oscillation frequency f rcclk and an rc constant is expressed by the following equation: 1 f rcclk = t rcclk =k rcclk ?r?c where t rcclk is the period of the oscillator clock, k rcclk the proportional constant, and r x c the product of capacitances cs, ct, (cs+cvr) and (ct+cvr) and resistances rs and rt. the value of k rcclk slightly changes depending on the value of the supply voltage vdd, ri, r, or c. table 21-2 lists the typical k rcclk values. table 21-2 typical values of the proportional constant k rcclk of rc oscillator circuits v dd (v) csn, ctn (pf) cvrn(pf) rsn, rtn (k ? ) k rcclk (typ.) 3 560 820 10 1.26 560 820 100 1.24 3 560 820 15 1.25 560 820 105 1.24 1.5 560 820 15 1.26 560 820 105 1.22 note) n=0,1 note: out of the port 3 and port 4 pins, pins that are to be us ed for the rc-adc function must be configured as secondary function input or output using the mode register (p3mod0, p4mod0, p4mod1) of the corresponding port. all the port 3 pins except p35/rcm (see section 21.1.3, ?list of pins?) are configured as pins dedicated to the rc-adc function during a/d conversion. therefore, all the port 3 pins except p35 cannot be used as their primary functions in oscillation mode no. 0, 1, 2, 3 or 4, which is selected by the radmod register. in the same way, the p44 to p47 pins of port 4 cannot be used as their primary func tions in oscillation mode no. 5, 6 or 7. figures 21-2 to 24-5 show the oscillator circuit configurati ons, the modes of oscillation fo r each configuration, and the om3?0 bit settings. om3 om2 om1 om0 oscillation mode 0 0 0 1 oscillates with the reference resistor rs0 and cs0 0 0 1 0 oscillates with the sensor rt0 and cs0 figure 21-2 when rcosc0 is used for measurement with one resistive sensor note: the unused pin rct0 shown in figure 21-2 is configured as a pin dedicated to the rc-adc function during a/d conversion; therefore, during a/d conversion, rct0 cannot be used as a primary function port (p34). cs0 rs0 rt0 rct0 in0 cs0 rs0 rt0
ml610q407/ml610q408/ml610q409 user's manual chapter 21 rc oscillation type a/d converter 21-10 om3 om2 om1 om0 oscillation mode 0 0 0 1 oscillates with the reference resistor rs0 and cs0 0 0 1 0 oscillates with the sensor rt0 and cs0 0 0 1 1 oscillates with the reference resistor rt 0-1 and cs0 figure 21-3 when rcosc0 is used for measurement with one resistive sensor (two points are adjusted with two reference resistors) om3 om2 om1 om0 oscillation mode 0 0 0 1 oscillates with the reference resistor rs0 and cs0 0 1 0 0 oscillates with the sensor rs0 and ct0 figure 21-4 when rcosc0 is used for m easurement with one capacitive sensor note: the unused pin rt0 shown in figure 21-4 is configured as a pin dedicated to the rc-adc function during a/d conversion; therefore, during a/d conversion, rt0 cannot be used as a primary function port (p33). om3 om2 om1 om0 oscillation mode 0 1 0 1 oscillates with the reference resistor rs1 and cs1 0 1 1 0 oscillates with the sensor rt1 and cs1 figure 21-5 when rcosc1 is used for measurement with one resistive sensor cs0 rs0 rt0 rct0 in0 cs0 rs0 ct0 cs0 rs0 rt0 rct0 in0 cs0 rs0 rt0 rt 0-1 cs1 rs1 rt1 in1 cs1 rs1 rt1
ml610q407/ml610q408/ml610q409 user's manual chapter 21 rc oscillation type a/d converter 21-11 21.3.2 counter a/counter b reference modes there are the following two modes of rc-adc conversion operation: ?counter a reference mode (radmod radi = ?0?) in this mode, a gate time is determined by counter a and th e base clock (bsclk), which is used as the time reference, then the rc oscillator clock (rcclk) is counted by counter b within the gate time to ma ke the content of counter b the a/d conversion value. the a/d conversion value is propor tional to rc oscillation frequency. ?counter b reference mode (radmod radi = ?1?) in this mode, a gate time is determined by counter b and the rc oscillator clock (rcclk), and the base clock (bsclk), which is used as the time reference, is counted by counter a within the gate time to make the content of counter a the a/d conversion value. the /d conversion value is inversely proportional to rc oscillation frequency. (1) operation in counter a reference mode figure 21-6 shows the operation timing in counter a reference mode. following is an example of operation procedure in counter a reference mode: c preset to counter a (radca1 and radca0) the value obtained by subtracting the count value ?na0? from the maximum value + 1 (10000h). the product of the count value ?na0? and the bsclk clock cycle indicates the gate time. d preset ?0000h? to counter b (radcb1 and radcb0). e set the om3?om0 bits of radmod to desired oscillation mode. (see table 21-1.) f set the radi bit of radmod to ?0? to specify generating of an interrupt request signal by counter a overflow. g set the rarun bit of radcon to ?1? to start a/d conversion. counter a starts counting of the base clock (bsclk) when rarun is set to ?1? and the rcon signal (signal synchronized with the fall of the base clock) is set to ?1?. when counter a overflows, the rarun bit is automatically reset to ?0? ( h ) and counting is terminated. at the same time, an rc-adc interrupt request (radin) occurs ( i ). when the rcon signal is set to ?1?, the rc oscillator circu it starts operation and counter b starts counting of the rc oscillator clock (rcclk). when the rarun bit is reset to ?0? due to overflow of counter a, rc oscillation stops and counter b stops counting. the final count value ?nb0? of counter b is th e rcclk count value during the gate time ?na0 x t bsclk ? and is expressed by the following expression: t bsclk nb0 ? na0 ? t rcclk f rcclk where t bsclk indicates the bsclk period and t rcclk the rcclk period. that is, ?nb0? is a value proportional to the rc oscillation frequency f rcclk .
ml610q407/ml610q408/ml610q409 user's manual chapter 21 rc oscillation type a/d converter 21-12 (10000h ? na0) (+1) (+2) (+3) 0fffch 0000h t bs cl k h overflow gate time na0t bsclk c 0000h 0001h 0002h nb0 ? 2nb0 ? 1 nb0 d nb0t rcclk i (interrupt request) t rcclk rarun bsclk rcon counter a cr oscillator circuit input waveform in0/in1 rccl k counter b r adint na0: reference count value nb0: measurement count value g 0ff fdh 0fffeh 0ffffh figure 21-6 operation timing in counter a reference mode (2) operation in counter b reference mode figure 21-7 shows the operation timing in counter b reference mode. following is an example of operation procedure in counter b reference mode: c preset to counter b (radcb1 and radcb0) the value obtained by subtracting the count value ?nb1? from the maximum value + 1 (10000h). the product of the count valu e ?nb1? and the rcclk clock cycle indicates the gate time. d preset ?0000h? to counter a (radca1 and radca0). e set the om3?om0 bits of radmod to desired oscillation mode. (see table 21-1.) f set the radi bit of radmod to ?1? to specify generating of an interrupt request signal by counter b overflow. g set the rarun bit of radcon to ?1? to start a/d conversion. when the rarun bit is set to ?1? and the rcon signal (signal synchronized with the fall of the base clock) is set to?1?, the rc oscillator circuit starts operation and counter b st arts counting of the rc oscillator clock (rcclk). when counter b overflows, the rarun bit is automatically reset ( h ) and conversion operation terminates. at the same time, an rc-adc interrupt reque st (radint) occurs. ( i ) when the rcon signal is set to ?1?, counter a starts counting of the base clock (bsclk). when the rarun bit is reset due to overflow of counter b, counter a stops counting. the final count ?na1? of counter a is the clk count value during the gate time ?nb1 x t rcclk ? and is expressed by the following expression: t rcclk 1 na1 ? nb1 ? t bsclk f rcclk
ml610q407/ml610q408/ml610q409 user's manual chapter 21 rc oscillation type a/d converter 21-13 that is, ?na1? is a value inversely pr oportional to the rc oscillation frequency f rcclk . 0000h 0001h 0002h 0003h na1 ? 2 na1 ? 1 na1 t bsclk g h na1 x t bsclk d (10000h ? nb1) (+1) (+2) 0fffehh 0ffffhh 0000h c nb1 x t rcclk gate time i (interrupt request) t rcclk rarun bscl k rcon counter a rc oscillator circui t input wavefor m in0/in1 rccl k counter b radint na1: measurement count value nb1: reference count value 0fffdh overflow na1 ? 3 figure 21-7 operation timing in counter b reference mode
ml610q407/ml610q408/ml610q409 user's manual chapter 21 rc oscillation type a/d converter 21-14 21.3.3 example of use of rc oscillation type a/d converter this section describes the method of performing a/d conversi on for sensor values in counter a and b reference modes by taking temperature measurement by a thermistor as an example. figure 21-8 shows the circuit configuration of 1-thermistor rc oscillator circuit using rcosc0. figure 21-8 configuration of 1-thermi stor rc oscillator circuit using rcosc0 figure 21-9 shows the temperature characteris tics of the thermistor resistance rt0. thermistor resistance rt0 temperature t rt0 = f(t) digital value nt0 rt0 nt0 = k?rt0 = k?f(t) figure 21-9 temperature characteristics of thermistor characteristics figure 21-10 a/d conversion (ideal characteristics when nt0 is proportional to rt0) rt0 is expressed as a function of temperature t by the following equation: rt0 = f (t) figure 21-10 shows the ideal characteristic s of a/d conversion with the assumpti on that rt0 is an analog quantity. in the ideal characteristics, the a/d conversion value nt 0 will purely depend on rt0 only. assuming that nt0 is proportional to rt0, let proportional constant be k, then nt0 has the following relationship with temperature t: nt0 = k ? rt0 = k ? f (t) ... expression a therefore, temperature t can be expressed as a digital va lue by performing the conversi on processing that accords with the characteristics shown in figure 21-9 for nt0 by software. to convert from an rt0 value to a digita l value, the ratio is used between a) the oscillation frequency by the thermistor connected to the rt0 pin and the capacitor connected to the cs0 pin and b) the oscillation frequency by the reference resistor (which ideally should have no temperature character istics) connected to the rs0 pin and the capacitor connected to the cs0 pin. this is for making the conditions other than resistance equal to eliminate the error factor in oscillation characteristics. as shown in figures 21-9 and 21-11, the rt0 value depends on temperature t and the rs0 value is assumed to be constant regardless of temperature t. it is ideal if the characteristics of the oscillation frequency f osc to temperature t using these resistances will be like the solid lines in figures 21-12 and 21-13; however, in reality, it would appear that they will be like the dotted lines due to error factors such as ic temperature characteristics. since the condition of f rcclk (rt0) and that of f rcclk (rs0) are the same except for th e resistances, the error ratios are almost the same; therefore, errors can almost be eliminated by using the ratio between f rcclk (rt0) and f rcclk (rs0). cs0 rs0 rt0 in0 cs0 reference resisto r thermistor rt0
ml610q407/ml610q408/ml610q409 user's manual chapter 21 rc oscillation type a/d converter 21-15 the ratio between f rcclk (rt0) and f rcclk (rs0) is equivalent to the above-m entioned a/d conversion value nt0 that should ideally depend only on rt0. reference resistance rs0 temperature t f rcclk (rt0) temperature t ideal includes errors due to factors other t han rt0 f rc lk (rs 0) = k rc clk (cs0+cvr)rt0 1 figure 21-11 temperature characteristics of reference resistor figure 21-12 oscillation characteristics of thermistor temperature t includes errors due to factors other than rt0 f rcc lk (rs 0) = k rcclk (cs0+cvr)rs0 1 ideal f rclk (rs 0) figure 21-13 oscillation characteristics of reference resistor figure 21-14 shows, as an example of method, a timing chart of one cycle of conversion from analog value rt0 to a digital value, that is, a/d conversion. basically, one a/d conversion cycle must consist of two st eps, as shown in figure 21-14. the reason for requiring two steps is that the reference resistor and the thermistor must first be oscillated separately and then the ratio between the oscillation frequencies of them is used, as described above. in the example below, operation for these two steps is performed using the following combination: ?first step = rc oscillation with rs0 in counter a reference mode ?second step = rc oscillation with rt0 in counter b reference mode besides this, there would be several possible a/d conversion methods. in the above method, the operation time (gate time) for the s econd step fluctuates depending on the value of thermistor rt0. to avoid the fluctuation of the operation time, using a method that uses the following combination is recommended: ?first step = rc oscillation with rs0 in counter b reference mode ?second step = rc oscillation with rt 0 in counter a reference mode a/d conversion procedure is explained below by taking figure 21-14 as an example.
ml610q407/ml610q408/ml610q409 user's manual chapter 21 rc oscillation type a/d converter 21-16 (b ) 32.768 khz c base clock bsclk 0 1h radmod (bits 4?0) f 01h (erad=1) radcon (b it 0 ) g (c ) 00h j k 00h (f) 12h cr oscillating state (c ros c0) stop stop oscillates with rs0 stop (counter a reference mode) (counter b reference mode) 0.366 sec na0t bsclk =nb0t rc clk (rs0) nb0trcclk(rt0)=na1t bsclk (increments by bsclk) cnta2?0 0000h ( increments by bsclk ) na1 0fb50h d (increments by rcc lk (rs0)) cntb2 ? 0 0000h 0000h e nb0 (incr ements by rcclk (rt0)) 10000h ? nb0 int generated (a) (d) rc-adc interrupt request radint (e) l h hlt overflow i int generated note) na0=4b0h, t sysclk =1/ 32768 hz; c to l : software processing; (a) to (f): hardware processing overflow 00h 01h (erad=1) oscillates with rs0 figure 21-14 timing chart for 1 cycle of a/d conversion (example) c set the base clock to 32.768 khz. (write ?00h? in fcon0.) d preset ?10000h ? na0? in counter a. e preset ?0000h? in counter b. f write ?01h? in radmod to select c ounter a reference mode and the osc illation mode that uses reference resistance rs0. g write ?01h? in radcon to start a/d conversion operation. h write ?1? in the hlt bit of sbycon to set the device to halt mode. note: in this example, na0 is set to 4b 0h because the gate time ?na0 x t bsclk ? in oscillation mode with refe rence resistor rs0 is set to 0.366 second. the value of na0 is related to how much the margin of the quantization error of the a/d conversion is: the greate r the na0 value is, the smaller the margin of error becomes. to reduce noise contamination to the rc oscillator circuit cause d by cpu operation, it is recommended to constantly put the device into halt mode during operation of rc oscillation. from this point of time, the rc osc illator circuit (rcosc0) continues osc illation for about 0.366 second with the reference resistance rs0. then, when counter a overflows, the radint signal is set to ?1? and an rc-adc interrupt cnta1-0 cntb1-0
ml610q407/ml610q408/ml610q409 user's manual chapter 21 rc oscillation type a/d converter 21-17 request is generated. (section (a)). also , the generation of interrupt request rel eases halt mode (section (b)) and at the same time, a/d conversion operation stops. (section (c), rarun bit = "0"). at this time, counter a is set to ?0000h?. the content of counter b at this time is expressed by the following expression: t bsclk nb0 = na0 ? t rcclk (rs0) ... expression b that completes the operations in first step. c calculate ?10000h ? nb0? from the content of counter b ?nb0? and set the obtained value in counter b. at this point, counter a needs to be cleared; however, no processing is required since the counter is already set to ?0000h?. d write ?12h? in radmod to select count er b reference mode and the oscillati on mode that uses thermistor rt0. e write ?01h? in radcon to start a/d conversion operation. f write ?1? in the hlt bit of sbycon to set the device to halt mode. the rc oscillator circuit (rcosc0) oscilla tes with thermistor rt0 from this point until counter b overflows. this period is equal to the product of ?nb0? obtained in the first step and the oscillation period t rcclk (rt0) using rt0. when counter b overflows, the radint signal is set to ?1? a nd an rc-adc interrupt request is generated. (section (d)). also, the generation of interrupt request releases halt mode (section (e)) and at the same time, a/d conversion operation stops. (section (f), rarun bit = "0"). this completes the operations in second step. the content of counter a at this time becomes the a/d conversion value na1, which is expressed by the following expression: t rcclk (rt0) na1 = nb0 ? t bsclk ... expression c from expressions b and c, na1 is e xpressed by the following expression: t rcclk (rt0) na1 = na0 ? t rcclk (rs0) ... expression d where t rcclk (rs0) is the oscillator clock period by reference resistor rs0 and t rcclk (rt0) the oscillator clock period by thermistor rt0. since the oscillation period is expressed by "t rcclk = k rcclk x r x c", t rcclk (rs0) and t rcclk (rt0) are expressed by the following expressions: t rcclk (rs0) = k rcclk ? (cs0+cvr) ? rs0 ... expression e t rcclk (rt0) = k rcclk ? (cs0+cvr) ? rt0 when expression e is substituted for expression d, na1 will be: rt0 na1 = na0 ? rs0 since ?na0? (?4b0h? in this example) and rs0 are consta nts whose values are fixed, ?na1? is a digital value proportional to rt0. this very ?na1? corresponds to ?nt0? in expression a. that concludes the description of the a/d conversion met hod using a thermistor. ?na1? that has been obtained must further be converted to a value such as a temperature i ndication value for thermometer by program according to the temperature-to-resistance charact eristics of the thermistor.
ml610q407/ml610q408/ml610q409 user's manual chapter 21 rc oscillation type a/d converter 21-18 21.3.4 monitoring rc oscillation the rc oscillator clock (rcclk) can be out put using the secondary f unction of the p35 pin of port 3. see chapter 20, ?port 3,? for the details of the secondary function of p35. monitoring rc oscillation is useful for checking the characteristics of the rc oscillator circuit. that is, the relationship between a sensor, such as a thermistor, and the oscillation frequency can be measured. for instance, the coefficient for conversion from the above-described na1 value to a temper ature indication value can be obtained by checking the relationship between the ambient temperature of a thermistor-incorporated rc oscillator circuit, the oscillation frequency with thermistor rt0, and the oscillation frequency with reference resistor rs0. note: p35 (rcm) is a monitor pin for oscillation clock. the channel 0 and channel 1 share the monitor pin. please use p35 (rcm) for the evaluation purpose and disable the output while operating in an actual application to minimize the noise.
ml610q407/ml610q408/ml610q409 user's manual chapter 21 rc oscillation type a/d converter 21-19 21.4 specifying port registers to enable the rc-adc function, the applicable bit of each related port register needs to be set. see chapter 16, ?port 3? and chapter 18, ?port 4? for detail about the port registers. 21.4.1 functioning p35(rcm), p34(rct0), p33(rt0), p32(rs0), p31(cs0) and p30(in0) as the rc-adc(ch0) set p35md0-p30md0(bit5-bit0 of p3mod0 register) to ?1?, for specifying the rc-adc as the secondary function of p35, p34, p33, p32, p31 and p30. register name p3mod0 register (address: 0f21ch) bit 7 6 5 4 3 2 1 0 bit name p37md0 p36md0 p35md0 p34md0 p33md0 p 32md0 p31md0 p30md0 setting value - - 1 1 1 1 1 1 set the p34c1 to p30c1 bits (p3con1 register bits 4 to 0) to ?0?, the p34c0 to p30c0 bits (p3con0 register bits 4 to 0) to ?0?, and the p34dir to p30dir bits (p3dir register bits 4 to 0) to ?1? for selecting the state mode of the p34, p33, p32, p31, and p30 to high-impedance input. the p34c1-p30c1 bit and p34c0-p30c0 bit can be set to all ?1? instead of all ?0? to select the high-impedance inputs. set the p35c1 bit (p3con1 register bit 5) to ?1?, the p35c0 bit (p3con0 register bit 5) to ?1?, and the p35dir bit (p3dir register bit 5) to ?0? for selecting the p35 state mode to cmos output. register name p3con1 register (address: 0f21bh) bit 7 6 5 4 3 2 1 0 bit name p37c1 p36c1 p35c1 p34c1 p33c1 p32c1 p31c1 p30c1 setting value - - 1 0 0 0 0 0 register name p3con0 register (address: 0f21ah) bit 7 6 5 4 3 2 1 0 bit name p37c0 p36c0 p35c0 p34c0 p33c0 p32c0 p31c0 p30c0 setting value - - 1 0 0 0 0 0 register name p3dir register (address: 0f219h) bit 7 6 5 4 3 2 1 0 bit name p37dir p36dir p35dir p34dir p33dir p32dir p31dir p30dir setting value - - 0 1 1 1 1 1 data of p35d-p30d bits (bit5-0 of p3d register) do not affect to the rc-adc function, so don?t care the data for the function. register name p3d register (address: 0f218h) bit 7 6 5 4 3 2 1 0 bit name p37d p36d p35d p34d p33d p32d p31d p30d setting value - - ** ** ** ** ** ** - : bit that does not exist
ml610q407/ml610q408/ml610q409 user's manual chapter 21 rc oscillation type a/d converter 21-20 * : bit not related to the rc-adc function ** : don?t care 21.4.2 functioning p47(rt1), p46(rs1), p45( cs1) and p44(in1) as the rc-adc(ch1) set p47md1-p44md1 bits(bit7-bit4 of p4mod1 register) to ?0? and set p47md0-p44md0(bit7-bit4 of p4mod0 register) to ?1?, for specifying the rc-adc as th e secondary function of p47, p46, p45 and p44. register name p4mod1 register (address: 0f225h) bit 7 6 5 4 3 2 1 0 bit name p47md1 p46md1 p45md1 p44md1 p43md1 p42md1 p41md1 p40md1 setting value 0 0 0 0 * * * * register name p4mod0 register (address: 0f224h) bit 7 6 5 4 3 2 1 0 bit name p47md0 p46md0 p45md0 p44md0 p43md0 p42md0 p41md0 p40md0 setting value 1 1 1 1 * * * * set the p47c1 to p44c1 bits (p4con1 register bits 7 to 4) to ?0?, the p47c0 to p44c0 bits (p4con0 register bits 7 to 4) to ?0?, and the p47dir to p44dir bits (p4dir register bits 7 to 4) to ?1? for selecting the state mode of the p47, p46, p45, and p44 to high-impedance input. the p47c1-p44c1 bit a nd p47c0-p44c0 bit can be set to all ?1? instead of all ?0? to select the high-impedance inputs. register name p4con1 register (address: 0f223h) bit 7 6 5 4 3 2 1 0 bit name p47c1 p46c1 p45c1 p44c1 p43c1 p42c1 p41c1 p40c1 setting value 0 0 0 0 * * * * register name p4con0 register (address: 0f222h) bit 7 6 5 4 3 2 1 0 bit name p47c0 p46c0 p45c0 p44c0 p43c0 p42c0 p41c0 p40c0 setting value 0 0 0 0 * * * * register name p4dir register (address: 0f221h) bit 7 6 5 4 3 2 1 0 bit name p47dir p46dir p45dir p44dir p43dir p42dir p41dir p40dir setting value 1 1 1 1 * * * * data of p47d-p44d bits (bit7-4 of p4d register) do not affect to the rc-adc function, so don?t care the data for the function.
ml610q407/ml610q408/ml610q409 user's manual chapter 21 rc oscillation type a/d converter 21-21 register name p4d register (address: 0f220h) bit 7 6 5 4 3 2 1 0 bit name p47d p46d p45d p44d p43d p42d p41d p40d setting value ** ** ** ** * * * * * : bit not related to the rc-adc function ** : don?t care note: status of output pins p31-p 34 and p45-p47 changes according to the rc osc illation mode specified by om0-om3 bit of radmod register.
chapter 22 lcd drivers
ml610q407/ml610q408/ml610q409 user's manual chapter 22 lcd drivers 22-1 22. lcd driver 22.1 overview this lsi includes lcd drivers that display the contents that are set in the display register. for the ml610q407/q408/q409, the numbers of commons and se gments and the maximum number of dots are as shown in table 22-1. table 22-1 numbers of commons/segments and maximum number of dots for ml610q407/8/9 product name (ml610...) q407 q408 q409 2com-32seg 2com-36seg 2com-40seg 3com-31seg 3com-35seg 3com-39seg 4com-30seg 4com-34seg 4com-38seg number of commons/segments (changeable by software) 5com-29seg 5com-33seg 5com-37seg maximum number of dots 145 165 185 the lcd display function consists of four blocks as shown in figure 22-1: 1. display registers 2. display allocation 3. display control 4. driver figure 22-1 configuration of lcd display function the display registers are used to store the contents to be displayed as bit patterns. the bit pattern storage method depends on the specification of the lcd panel to be used (display pattern and assignment of the com pin and seg pin) and the setting of the display allocation circuit. the display allocation block controls mapping of the display register for the lcd common/segment. using the display allocation registers a and b or not using them is selectable. when using them (set dasn bit of dspmod1 register to ?1?), the segment mapping of the display register can be specified in bit units by programming according to the contents of di splay allocation registers a and b. therefore, the display register array can be changed in flexible and simplify the software pro cess for display (this function is defined as the programmable display allocation function in the user's manual). also, the data specified to the registers a and b can be easily prepared by using oki semiconductor lcd allocation tool. when the display allocation registers a and b are not used (set the dspmod1 register's dasn bit to "0"), the display content is controlled only with the display registers. the display control circuit generates lcd drive wave forms according to the char acteristics of the lcd. a bias, a bias voltage multiplying clock, a duty, and a frame frequency suitable for the lcd panel can be selected. dspr00 dspr01 dspr02 display registers #jbt 7pmubhfnvmujqmzjohdmpdl %vuz 'sbnfgsfrvfodz display allocation display control com pin seg pin lcd panel allocation registers a, b com driver seg driver driver 0 1 allocation register select by dasn bi t (dspmod1 register) dspr26 dspr27
ml610q407/ml610q408/ml610q409 user's manual chapter 22 lcd drivers 22-2 a) when not using programmable display allocation function (dasn bit of dspmod1 register is ?0?) suitable for the dot matrix type lcd panel whose common/segm ent array is approximated to the bit array of the display register. figure 22-2 shows an example of the correlation between the display registers and the dot matrix type lcd image. figure 22-2 example of correlation between di splay registers and dot matrix type lcd image b) when using programmable display allocation function (dasn bit of dspmod1 register is ?1?) the programmable display allocation function is suitable for the lcd panel of segment type or character type whose common/segment array is restricted by the design or wiring. the display allocation registers a and b can be used to programmatically specify the display register bit-by-bit. this allows the display registers to be arrayed flexibly and thus makes the display processing in the software easier. the cont ent of the display allocation register a (dsmcn) specifies the addresses of the display registers (dspr00 to 27) to be output to the common "n" of the segment "m." the content of the display allocation register b (dsmcnb) specifies the bits of the display registers (dspr00 to 27) to be output to the common "n" of the segment "m." figure 22-3 shows an example of the correlation between the display registers and the dot matrix type lcd image when the programmable display allocation is used. dspr bit symbol on panel com seg ? ? ? ? ? dspr4 6 4g 1 7 ? ? ? ? .. dspr0 2 0c 3 0 dspr0 1 0b 4 0 dspr0 0 0a 4 1 figure 22-3 an example of correlation bet ween display registers and segment type lcd seg0 dspr0 fixed display allocation c o m 0 c o m 1 c o m 2 dspr1 dspr2 dspr3 dspr4 b i t 0 b i t 1 seg1 seg2 seg3 dspr26 dspr27 display registers b i t 2 b i t 3 b i t 4 b i t 5 b i t 6 b i t 7 c o m 3 c o m 4 seg39 seg4 dot matrix lcd seg38 com0 dspr00 programmabl e display allocation s e g 0 s e g 1 s e g 2 s e g 5 s e g 6 s e g 7 s e g 3 s e g 4 dspr01 dspr02 unused dspr04 b i t 0 b i t 1 com1 com3 dspr26 dspr27 display registers b i t 2 b i t 3 b i t 4 b i t 5 b i t 6 b i t 7 1e 1f 1h 2b 2a 2c 2d 2e 2f 2g 2h 4a 4b 4c 4d 4e 4f 4g 4h com4 0h 0g 0f 0e 0d 0c 0b 0a 1h 1g 1f 1e 1d 1c 1b 1a 2h 2g 2f 2e 2d 2c 2b 2a 4h 4g 4f 4e 4d 4c 4b 4a 0b 0c 1a 1d 0h 0e 0a 0f 0g 1b 1c 0d 1g ? ? ? ? s e g 39
ml610q407/ml610q408/ml610q409 user's manual chapter 22 lcd drivers 22-3 22.1.1 features the lcd drivers are applicable to various types of lcd panels. ? ml610q409: 185 dots max. (37 segments x 5 commons) ? ml610q408: 165 dots max. (33 segments x 5 commons) ? ml610q407: 145 dots max. (29 segments x 5 commons) ? 1/1 to 1/5 duty ? 1/2 or 1/3 bias (built-in bias generation circuit) ? frame frequency selectable (4 types) ? bias voltage multiplying clock selectable (8 types) ? programmable display allocation function the programmable display allocation function facilitates software display processing. by using ?all lcds on mode? and ?all lcds off mode?, lcd panel inspection processing software can be easily created. 22.1.2 configuration of the lcd drivers figure 22-4 shows the configuration of the lcd drivers and the bias generation circuit. biascon : bias circuit control register dspmod0 : display mode register 0 dspmod1 : display mode register 1 dspcon : display control register dsmcn : allocation register (m = 0 to 39, n = 0 to 4) dspr00 - dspr27 : display registers figure 22-4 configuration of lcd drivers and bias generation circuit v ss c2 c1 c 12 data bus dspr00 ? dspr27 common driver com0 segment driver seg0 dspmod0 dspmod1 dspcon dsmcn display allocation control circuit biascon com1 4 seg39 36 v dd v dd v ddl cl 7pmubhf sfhvmbups djsdvju v l2 cb v l3 cc v l1 bias generation circuit
ml610q407/ml610q408/ml610q409 user's manual chapter 22 lcd drivers 22-4 22.1.3 configuration of the bias generation circuit the bias generation circuit generates lcd drive voltages (v l1 to v l3) by multiplying the power supply voltage (v dd ) or the voltage (v ddl ) generated by the voltage regulator circuit with the capacitor (c 12 ). when a system reset starts the bias generation circuit operation stops. figure 22-5-1 and 22-5-2 show the configur ation of the bias generation circuit. figure 22-5-1 configuration of bi as generation circuit (1/3 bias) bias generation circuit v dd v ss bias circuit on selected (bson) to lcd driver (v l1 to v l3 ) vdd = 1.25 to 3.6v, with lcd re g ulato r v dd 7pmubhfsfhvmbups djsdvju v ddl cl v l3 v l2 cc cb v l1 c2 c1 c 12 bias generation circuit v ss c2 c1 c 12 bias circuit on selected (bson) to lcd driver (v l1 to v l3 ) vdd = 2.4 to 3.6v, without lcd v l3 v l2 v l1 ca cb v dd bias generation circuit v ss c2 c1 c 12 bias circuit on selected ( bson ) to lcd driver (v l1 c v l3 ) vdd = 1.6 to 3.6v, without lcd v l3 v l2 v l1 cc ca v dd
ml610q407/ml610q408/ml610q409 user's manual chapter 22 lcd drivers 22-5 figure 22-5-2 configuration of bi as generation circuit (1/2 bias) bias generation circuit v dd v ss bias circuit on selected (bson) to lcd driver (v l1 to v l3 ) vdd = 1.25 to 3.6v, with lcd re g ulato r v dd 7pmubhfsfhvmbups djsdvju v ddl cl v l3 v l2 cc v l1 c2 c1 c 12 bias generation circuit v ss c2 c1 c 12 bias circuit on selected (bson) to lcd driver (v l1 to v l3 ) vdd = 2.4 to 3.6v, without lcd v l3 v l2 v l1 ca v dd
ml610q407/ml610q408/ml610q409 user's manual chapter 22 lcd drivers 22-6 22.1.4 list of pins pin name input/output func tion ml610q407 ml610q408 ml610q409 v l1 ? power supply pin for lcd bias (internally generated) z z z v l2 ? power supply pin for lcd bias (internally generated) z z z v l3 ? power supply pin for lcd bias (internally generated) z z z c1 ? capacitor connection pin for lcd bias generation z z z c2 ? capacitor connection pin for lcd bias generation z z z com0 o lcd common pin z z z com1 o lcd common pin z z z com2/seg0 o lcd common/segment pin z z z com3/seg1 o lcd common/segment pin z z z com4/seg2 o lcd common/segment pin z z z seg3 o lcd segment pin z z z seg4 o lcd segment pin z z z seg5 o lcd segment pin z z z seg6 o lcd segment pin z z z seg7 o lcd segment pin z z z seg8 o lcd segment pin z z z seg9 o lcd segment pin z z z seg10 o lcd segment pin z z z seg11 o lcd segment pin z z z seg12 o lcd segment pin z z z seg13 o lcd segment pin z z z seg14 o lcd segment pin z z z seg15 o lcd segment pin z z z seg16 o lcd segment pin z z z seg17 o lcd segment pin z z z seg18 o lcd segment pin z z z seg19 o lcd segment pin z z z seg20 o lcd segment pin z z z seg21 o lcd segment pin z z z seg22 o lcd segment pin z z z seg23 o lcd segment pin z z z seg24 o lcd segment pin z z z seg25 o lcd segment pin z z z seg26 o lcd segment pin z z z seg27 o lcd segment pin z z z seg28 o lcd segment pin z z z seg29 o lcd segment pin z z z seg30 o lcd segment pin z z z seg31 o lcd segment pin z z z seg32 o lcd segment pin z z seg33 o lcd segment pin z z seg34 o lcd segment pin z z
ml610q407/ml610q408/ml610q409 user's manual chapter 22 lcd drivers 22-7 pin name input/output func tion ml610q407 ml610q408 ml610q409 seg35 o lcd segment pin z z seg36 o lcd segment pin z seg37 o lcd segment pin z seg38 o lcd segment pin z seg39 o lcd segment pin z
ml610q407/ml610q408/ml610q409 user's manual chapter 22 lcd drivers 22-8 22.2 description of registers 22.2.1 list of registers address name symbol (byte) symbol (word) r/w size initial value 0f0f0h bias circuit control register biascon ? r/w 8 38h 0f0f2h display mode regist er 0 dspmod0 r/w 8/16 00h 0f0f3h display mode register 1 dspmod1 dspmod r/w 8 00h 0f0f4h display control register dspcon ? r/w 8 00h 0f100h to 0f127h display register 00 to display register 27 dspr00 to dspr27 ? r/w 8 undefined 0f400h to 0f427h ds0c0a to ds39c0a ? r/w 8 undefined 0f440h to 0f467h ds0c1a to ds39c1a ? r/w 8 undefined 0f480h to 0f4a7h ds0c2a to ds39c2a ? r/w 8 undefined 0f4c0h to 0f4e7h ds0c3a to ds39c3a ? r/w 8 undefined 0f500h to 0f527h display allocation register a ds0c4a to ds39c4a ? r/w 8 undefined 0f600h to 0f627h ds0c0b to ds39c0b ? r/w 8 undefined 0f640h to 0f667h ds0c1b to ds39c1b ? r/w 8 undefined 0f680h to 0f6a7h ds0c2b to ds39c2b ? r/w 8 undefined 0f6c0h to 0f6e7h ds0c3b to ds39c3b ? r/w 8 undefined 0f700h to 0f727h display allocation register b ds0c4b to ds39c4b ? r/w 8 undefined
ml610q407/ml610q408/ml610q409 user's manual chapter 22 lcd drivers 22-9 22.2.2 bias circuit control register 0 (biascon) address: 0f0f0h access: r/w access size: 8-bit initial value: 38h 7 6 5 4 3 2 1 0 biascon ? ? bsel1 bsel0 bsn2 bsn1 bsn0 ? r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 1 1 1 0 0 0 biascon is a special function register (sfr) to control the bias generation circuit. [description of bits] ? bsn2-bsn0 (bit 3 to 1) the bsn2 to bsn0 bits are used to select a clock for multiplying the bias voltage in the bias generation circuit. lsclk to 1/128lsclk can be selected. bsn2 bsn1 bsn0 descri p tion 0 0 0 1/1 lsclk ( 32khz ) 0 0 1 1/2 lsclk ( 16khz ) 0 1 0 1/4 lsclk ( 8khz ) 0 1 1 1/8 lsclk ( 4khz ) 1 0 0 1/16 lsclk ( 2 khz ) ( initial value ) 1 0 1 1/32 lsclk ( 1khz ) 1 1 0 1/64 lsclk ( 512hz ) 1 1 1 1/128 lsclk ( 256hz ) ? bsel (bit 5 to 4) the bsel bit is used to set the bias in the bias generation circuit. 1/2 bias or 1/3 bias can be selected. bsel1 bsel0 descri p tion 0 0 1/3 bias 0 1 settin g p rohibited 1 0 settin g p rohibited 1 1 1/2 bias ( initial value )
ml610q407/ml610q408/ml610q409 user's manual chapter 22 lcd drivers 22-10 22.2.3 display mode register 0 (dspmod0) address: 0f0f2h access: r/w access size: 8/16 bit initial value: 00h 7 6 5 4 3 2 1 0 dspmod0 ? frm1 frm0 ? ? duty2 duty1 duty0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 dspmod0 is a special function register (sfr) to control the display mode of the lcd drivers. [description of bits] ? duty2 to duty0 (bit 2 to 0) the duty2 to duty0 bits are used to specify the duty in 5 steps (1/1 to 1/5). the numbers of commons/segments are determined according to the duty setting. product (ml610...) common to all products 407 408 409 duty2 duty1 duty0 duty number of commons/segments 0 0 0 1/1 duty (initial val ue) 2c-32s 2c-36s 2c-40s 0 0 1 1/2 duty 2c-32s 2c-36s 2c-40s 0 1 0 1/3 duty 3c-31s 3c-35s 3c-39s 0 1 1 1/4 duty 4c-30s 4c-34s 4c-38s 1 * * 1/5 duty 5c-29s 5c-33s 5c-37s ? frm1-frm0 (bit 6, 5) the frm1 to frm0 bits are used to select a frame frequency of the lcd drivers. the reference frequency of a frame frequency (llsclk = 32.768 khz) is selectable from 64 hz, 73 hz, 85 hz, or 102 hz. frm1 frm0 descri p tion 0 0 reference fre q uenc y : 64 hz ( initial value ) 0 1 reference fre q uenc y : 73 hz 1 0 reference fre q uenc y : 85 hz 1 1 reference fre q uenc y : 102 hz the frame frequency for each duty is listed in table 22-2. table 22-2 frame frequency for each duty frame frequency [hz] duty reference frequency 64hz reference frequency: 73 hz reference frequency: 85 hz reference frequency: 102 hz 1/1 duty 64.00 73.14 85.33 102.40 1/2 duty 64.00 73.14 85.33 102.40 1/3 duty 64.25 73.31 85.33 103.04 1/4 duty 64.00 73.14 85.33 102.40 1/5 duty 64.25 73.64 86.23 102.40
ml610q407/ml610q408/ml610q409 user's manual chapter 22 lcd drivers 22-11 22.2.4 display mode register 1 (dspmod1) address: 0f0f3h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 dspmod1 ? ? ? ? ? dasn ? ? r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 dspmod1 is a special function register (sfr) to control the display mode of the lcd drivers. use dspmod1 to select to use or unuse the programmable display allocation function for the display registers. [description of bits] ? dasn (bit 2) the dasn bit is used to control the operation of the programmable display allocation function. see sections 22.2.6, 22.2.7, and 22.3.3 for the programmable display allocation function. dasn descri p tion 0 not use pro g rammable dis p la y allocation function ( initial value ) 1 use pro g rammable dis p la y allocation function
ml610q407/ml610q408/ml610q409 user's manual chapter 22 lcd drivers 22-12 22.2.5 display control register (dspcon) address: 0f0f4h access: r/w access size: 8-bit initial value: 00h 7 6 5 4 3 2 1 0 dspcon ? ? ? ? ? ? lmd1 lmd0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 dspcon is a special functi on register (sfr) to control the lcd drivers. [description of bits] ? lmd1-lmd0 (bit 1, 0) the lmd1 and lmd0 bits are used to select an lcd display mode. lcd stop mode, all lcds off mode, lcd display mode, and all lcds on mode can be selected. in lcd stop mode, v ss level is output to all the common drivers and segment drivers. the charge and discharge current to and from the display panel can be stopped. in all lcds off mode, off waveform is output to all the segment drivers irrespective of the contents of the display registers. in lcd display mode, the contents of the disp lay registers are output to each segment driver. in all lcds on mode, on waveform is output to all the segm ent drivers irrespective of the contents of the display registers. lmd1 lmd0 descri p tion 0 0 lcd sto p mode ( initial value ) 0 1 all lcds off mode 1 0 lcd dis p la y mode 1 1 all lcds on mode
ml610q407/ml610q408/ml610q409 user's manual chapter 22 lcd drivers 22-13 22.2.6 display allocation register a (ds0c0a to ds39c4a) address: 0f400h to 0f427h, 0f440h to 0f467h, 0f480h to 0f4a7h, 0f4c0h to 0f4e7h, 0f500h to 0f527h access: r/w access size: 8-bit initial value: undefined 7 6 5 4 3 2 1 0 dsmcna ? ? a5 a4 a3 a2 a1 a0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 x x x x x dsmcna (m= 0 to 39, n = 0 to 4) are special function registers (sfrs) that are used for the programmable display allocation function. each valid bit of dsmcna becomes undefined at system reset. table 22-3 shows a list of the display allocation register a. [description of bits] ? a5 to a0 (bit 5 to 0) the a5 to a0 bits of dsmcna (m = 0 to 39, n = 0 to 4) are used to select the addresses of the display registers (dspr00 to 27) that are output to common n of segment m. set dsmcna when the dasn bit of the display mode register 1 (dspmod1) is ?0?. when the dasn bit is ?1?, access from the cpu is invalid.
ml610q407/ml610q408/ml610q409 user's manual chapter 22 lcd drivers 22-14 table 22-3 display allocation register a segment common register name address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w seg0 com0 ds0c0a 0f400h ? ? ? a4 a3 a2 a1 a0 r/w seg1 com0 ds1c0a 0f401h ? ? ? a4 a3 a2 a1 a0 r/w seg2 com0 ds2c0a 0f402h ? ? ? a4 a3 a2 a1 a0 r/w seg3 com0 ds3c0a 0f403h ? ? ? a4 a3 a2 a1 a0 r/w : : : : : : : : : : : : : seg39 com0 ds39c0a 0f427h ? ? ? a4 a3 a2 a1 a0 r/w seg0 com1 ds0c1a 0f440h ? ? ? a4 a3 a2 a1 a0 r/w : : : : : : : : : : : : : seg39 com1 ds39c1a 0f467h ? ? ? a4 a3 a2 a1 a0 r/w seg0 com2 ds0c2a 0f480h ? ? ? a4 a3 a2 a1 a0 r/w : : : : : : : : : : : : : seg39 com2 ds39c2a 0f4a7h ? ? ? a4 a3 a2 a1 a0 r/w seg0 com3 ds0c3a 0f4c0h ? ? ? a4 a3 a2 a1 a0 r/w : : : : : : : : : : : : : seg39 com3 ds39c3a 0f4e7h ? ? ? a4 a3 a2 a1 a0 r/w seg0 com4 ds0c4a 0f500h ? ? ? a4 a3 a2 a1 a0 r/w : : : : : : : : : : : : : seg39 com4 ds39c4a 0f527h ? ? ? a4 a3 a2 a1 a0 r/w
ml610q407/ml610q408/ml610q409 user's manual chapter 22 lcd drivers 22-15 22.2.7 display allocation register b (ds39c4b to ds49c7b) address: 0f600h to 0f627h, 0f640h to 0f667h, 0f680h to 0f6a7h, 0f6c0h to 0f6e7h, 0f700h to 0f727h access: r/w access size: 8-bit initial value: undefined 7 6 5 4 3 2 1 0 dsmcnb ? ? ? ? ? b2 b1 b0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 x x x dsmcnb (m= 0 to 39, n = 0 to 4) are special function registers (sfrs) to store segment allocation data. each valid bit of dsmcnb becomes undefined at system reset. table 22-4 shows a list of the display allocation register b. [description of bits] ? b2-b0 (bit 2 to 0) the b2 to b0 bits of dsmcnb (m = 0 to 39, n = 0 to 4) are used to set the bits of the display registers (dspr00 to 27) that are output to common n of segment m. set dsmcnb when the dasn bit of the display control register 0 (dspcon0) is "0". when the dasn bit is ?1?, access from the cpu is invalid. b2 b1 b0 descri p tion 0 0 0 selects bit 0 0 0 1 selects bit 1 0 1 0 selects bit 2 0 1 1 selects bit 3 1 0 0 selects bit 4 1 0 1 selects bit 5 1 1 0 selects bit 6 1 1 1 selects bit 7
ml610q407/ml610q408/ml610q409 user's manual chapter 22 lcd drivers 22-16 table 22-4 display allocation register b segment common register name address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w seg0 com0 ds0c0b 0f600h ?????b2b1 b0 r/w seg1 com0 ds1c0b 0f601h ?????b2b1 b0 r/w seg2 com0 ds2c0b 0f602h ?????b2b1 b0 r/w seg3 com0 ds3c0b 0f603h ?????b2b1 b0 r/w : : : : : : : : : : : : : seg39 com0 ds39c0b 0f627h ?????b2b1 b0 r/w seg0 com1 ds0c1b 0f640h ?????b2b1 b0 r/w : : : : : : : : : : : : : seg39 com1 ds39c1b 0f667h ?????b2b1 b0 r/w seg0 com2 ds0c2b 0f680h ?????b2b1 b0 r/w : : : : : : : : : : : : : seg39 com2 ds39c2b 0f6a7h ?????b2b1 b0 r/w seg0 com3 ds0c3b 0f6c0h ?????b2b1 b0 r/w : : : : : : : : : : : : : seg39 com3 ds39c3b 0f6e7h ?????b2b1 b0 r/w seg0 com4 ds0c4b 0f700h ?????b2b1 b0 r/w : : : : : : : : : : : : : seg39 com4 ds39c4b 0f727h ?????b2b1 b0 r/w
ml610q407/ml610q408/ml610q409 user's manual chapter 22 lcd drivers 22-17 22.2.8 display registers (dspr00 to dspr27) address: 0f100h to 0f127h access: r/w access size: 8-bit initial value: undefined 7 6 5 4 3 2 1 0 dsprxx c7 c6 c5 c4 c3 c2 c1 c0 r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x dsprxx (xx = 00 to 27h) are special function registers (sfrs) to store display data. each valid bit of dsprxx becomes undefined at system reset. the display registers that are not used for lcd display can be used for data memories. set data in dsprxx before setting lcd display mode. the c4 to c0 values are used when the programmable display allocation function is not used. [description of bits] ? c7 to c0 (bit 7 to 0) the c7 to c0 bits are used to set display data. c7 c0 descri p tion 0 off waveform 1 on waveform
ml610q407/ml610q408/ml610q409 user's manual chapter 22 lcd drivers 22-18 table 22-5 list of display registers register name address corresponding segment bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w dspr00 0f100h seg0 c7 c6 c5 c4 c3 c2 c1 c0 r/w dspr01 0f101h seg1 c7 c6 c5 c4 c3 c2 c1 c0 r/w dspr02 0f102h seg2 c7 c6 c5 c4 c3 c2 c1 c0 r/w dspr03 0f103h seg3 c7 c6 c5 c4 c3 c2 c1 c0 r/w dspr04 0f104h seg4 c7 c6 c5 c4 c3 c2 c1 c0 r/w dspr05 0f105h seg5 c7 c6 c5 c4 c3 c2 c1 c0 r/w dspr06 0f106h seg6 c7 c6 c5 c4 c3 c2 c1 c0 r/w dspr07 0f107h seg7 c7 c6 c5 c4 c3 c2 c1 c0 r/w dspr08 0f108h seg8 c7 c6 c5 c4 c3 c2 c1 c0 r/w dspr09 0f109h seg9 c7 c6 c5 c4 c3 c2 c1 c0 r/w dspr0a 0f10ah seg10 c7 c6 c5 c4 c3 c2 c1 c0 r/w dspr0b 0f10bh seg11 c7 c6 c5 c4 c3 c2 c1 c0 r/w dspr0c 0f10ch seg12 c7 c6 c5 c4 c3 c2 c1 c0 r/w dspr0d 0f10dh seg13 c7 c6 c5 c4 c3 c2 c1 c0 r/w dspr0e 0f10eh seg14 c7 c6 c5 c4 c3 c2 c1 c0 r/w dspr0f 0f10fh seg15 c7 c6 c5 c4 c3 c2 c1 c0 r/w dspr10 0f110h seg16 c7 c6 c5 c4 c3 c2 c1 c0 r/w dspr11 0f111h seg17 c7 c6 c5 c4 c3 c2 c1 c0 r/w dspr12 0f112h seg18 c7 c6 c5 c4 c3 c2 c1 c0 r/w dspr13 0f113h seg19 c7 c6 c5 c4 c3 c2 c1 c0 r/w dspr14 0f114h seg20 c7 c6 c5 c4 c3 c2 c1 c0 r/w dspr15 0f115h seg21 c7 c6 c5 c4 c3 c2 c1 c0 r/w dspr16 0f116h seg22 c7 c6 c5 c4 c3 c2 c1 c0 r/w dspr17 0f117h seg23 c7 c6 c5 c4 c3 c2 c1 c0 r/w dspr18 0f118h seg24 c7 c6 c5 c4 c3 c2 c1 c0 r/w dspr19 0f119h seg25 c7 c6 c5 c4 c3 c2 c1 c0 r/w dspr1a 0f11ah seg26 c7 c6 c5 c4 c3 c2 c1 c0 r/w dspr1b 0f11bh seg27 c7 c6 c5 c4 c3 c2 c1 c0 r/w dspr1c 0f11ch seg28 c7 c6 c5 c4 c3 c2 c1 c0 r/w dspr1d 0f11dh seg29 c7 c6 c5 c4 c3 c2 c1 c0 r/w dspr1e 0f11eh seg30 c7 c6 c5 c4 c3 c2 c1 c0 r/w dspr1f 0f11fh seg31 c7 c6 c5 c4 c3 c2 c1 c0 r/w dspr20 0f120h seg32 c7 c6 c5 c4 c3 c2 c1 c0 r/w dspr21 0f121h seg33 c7 c6 c5 c4 c3 c2 c1 c0 r/w dspr22 0f122h seg34 c7 c6 c5 c4 c3 c2 c1 c0 r/w dspr23 0f123h seg35 c7 c6 c5 c4 c3 c2 c1 c0 r/w dspr24 0f124h seg36 c7 c6 c5 c4 c3 c2 c1 c0 r/w dspr25 0f125h seg37 c7 c6 c5 c4 c3 c2 c1 c0 r/w dspr26 0f126h seg38 c7 c6 c5 c4 c3 c2 c1 c0 r/w dspr27 0f127h seg39 c7 c6 c5 c4 c3 c2 c1 c0 r/w
ml610q407/ml610q408/ml610q409 user's manual chapter 22 lcd drivers 22-19 22.3 description of operation 22.3.1 operation of lcd drivers and bias generation circuit figure 22-6 shows the operation of the lcd drivers and the bias generation circuit. figure 22-6 operation of lcd drivers and bias generation circuit ? system reset causes the bias generation circu it and the lcd drivers to stop operation and v ss level to be output to each of the common and segment pins. ? by using the bias circuit control register (biascon), sel ect 1/2 bias or 1/3 bias and select the bias voltage multiplying clock. ? when the programmable display allocation function is used, set lcd allocation data in the display allocation registers (ds0c0 to ds39c4). ? set a frame frequency and a duty by using the disp lay mode register 0 (dspmod0). when using the programmable display allocation function, set the dspmod1 register's dasn bit to"1". when not using the programmable display allocation function, set the dspmod1 register's dasn bit to"0". ? set display data in the display registers (dspr00 to dspr27). ? on the display control register (dspcon), set the lmd1 and lmd0 bits to the display mode. (display waveform is output to each segment pin.) reset reset_n internal bias on signal lmd1, lmd0 lcd bias voltage v l1 v l3 common output com0 com4 segment output seg0 seg39 v ss v ss generation of lcd bias voltage common output waveforms segment output waveform c h defg
ml610q407/ml610q408/ml610q409 user's manual chapter 22 lcd drivers 22-20 22.3.2 segment mapping when the programmable display allocation function is not used the following shows the segment map of the display registers (dspr00 to 27) when the programmable display allocation function is not used (dspmod1 register's dasn bit = "0"): figure 22-7 segment map configuration diagram dspr00[3] seg0 com0 com1 com2 com3 dspr00[2] dspr00[1] dspr00[0] dspr01[3] dspr01[2] dspr01[1] dspr01[0] seg1 seg30 seg31 dspr1e[3] dspr1e[2] dspr1e[1] dspr1e[0] dspr1f[3] dspr1f[2] dspr1f[1] dspr1f[0] for ml610q407 dspr1f[4] dspr1e[4] ddspr01[4] dspr00[4] com4 dspr00[3] seg0 com0 com1 com2 com3 dspr00[2] dspr00[1] dspr00[0] dspr01[3] dspr01[2] dspr01[1] dspr01[0] seg1 seg34 seg35 dspr22[3] dspr22[2] dspr22[1] dspr22[0] dspr23[3] dspr23[2] dspr23[1] dspr23[0] for ml610q408 dspr23[4] dspr22[4] dspr01[4] dspr00[4] com4 dspr00[3] seg0 com0 com1 com2 com3 dspr00[2] dspr00[1] dspr00[0] dspr01[3] dspr01[2] dspr01[1] dspr01[0] seg1 seg38 seg39 dspr253] dspr24[2] dspr24[1] dspr23[0] dspr27[3] dspr27[2] dspr27[1] dspr27[0] for ml610q409 dspr27[4] dspr26[4] dspr01[4] dspr00[4] com4
ml610q407/ml610q408/ml610q409 user's manual chapter 22 lcd drivers 22-21 22.3.3 segment mapping when the programmable display allocation function is used when the programmable display allocation function is used (dasn bit of dspmod1 register is "1"), the segment map of the display registers (dspr00 to 27) can be programmatica lly changed using the display allocation registers (dsmcn: m = 0 to 39, n = 0 to 4). figure 22-8 shows the configuration when using the programmable display allocation function. figure 22-8 configuration when using the programmable display allocation function in the display allocation register a (dsmcna: m = 0 to 39, n = 0 to 4), set the address (00h to 27h) of the display register (dspr00 to dspr27) that is output to the common n of the segment n. in display allocation register b (dsmcnb: m = 0 to 39, n = 0 to 4), set the bits of the display register (dspr00 to dspr27) that is output to the common n of the segment m. for instance, to display bit 6 of display register 13 (dspr13) to the common 3 of the segment 6, set as follows. b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 ds6c3a * * 0 1 0 0 1 1 ds6c3b * * * * * 1 1 0 (0f4c6h) (0f6c6h) address specification of display register bit specification of display register "*" indicates an arbitrary value. [note] - set display allocation data to display allocation registers when the dasn bit of display mode register 1 (dspmod1) is "0". when the dasn bit is ?1?, access from the cpu is invalid. display allocation register a ds0c0a ds1c0a ds2c0a ds39c4a ds38c4a seg0-com0 mapping specification seg39-com4 mapping specification seg1-com0 mapping specification seg2-com0 mapping specification seg38-com4 mapping specification display allocation register b display registers ds0c0b ds1c0b ds2c0b ds39c4b ds38c4b dspr27 to dspr00 selecto r 8 6 3 segment driver 1 seg0 seg1 seg2 seg38 seg39 specify the display register's bit data bus 0f600h 0f601h 0f602h 0f727h 0f726h 0f400h 0f401h 0f402h 0f527h 0f526h specify the display register's address
ml610q407/ml610q408/ml610q409 user's manual chapter 22 lcd drivers 22-22 22.3.4 common output waveforms figure 22-9 shows the common output waveform at 1/5 duty (5 commons) and 1/3 bias. figure 22-9 common output waveform at 1/5 duty (5 commons) and 1/3 bias 0 1 2 3 0 1 com0 com1 com2 com3 v l3 v l2 v l1 v ss v l3 v l2 v l1 v ss v l3 v l2 v l1 v ss v l3 v l2 v l1 v ss frame frequenc y about 64hz/73hz/85hz/102hz 23 com4 v l3 v l2 v l1 v ss 44
ml610q407/ml610q408/ml610q409 user's manual chapter 22 lcd drivers 22-23 22.3.5 segment output waveform figure 22-10 shows the segment output waveform at 1/5 duty (5 commons) and 1/3 bias. figure 22-10 segment output waveform at 1/5 duty (5 commons) and 1/3 bias 0 1 2 3 0 1 2 4 segn segn ??? ??? v l3 v l2 v l1 v ss v l3 v l2 v l1 v ss frame frequenc y about 64hz/73hz/85hz/102hz ??? ??? 0 0 0 0 0 0 0 segn v l3 v l2 v l1 v ss segn v l3 v l2 v l1 v ss segn v l3 v l2 v l1 v ss segn v l3 v l2 v l1 v ss segn v l3 v l2 v l1 v ss segn v l3 v l2 v l1 v ss 1 data data data data data data da t a data 0 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 0 0 1 0 1 0 0 1 1 1 1 1 0 1 1 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 4 ??? ??? 0 0 0 0 0 1 1 1 3 0 0 0 0 1 1 1 1
chapter 23 power supply circuit
ml610q407/ml610q408/ml610q409 user's manual chapter 23 power supply circuit 23-1 23. power supply circuit 23.1 overview this lsi includes a voltage regulator circuit for internal logic (vrl). the vrl outputs the operating voltage, v ddl , of the internal logic circuit, program memory, ram, low-speed oscillation, etc. for the circuit configuration of the power supplies for lcd (v l1 to v l3 ), see chapter 22, ?lcd driver?. 23.1.1 features ? the vrl outputs the operating voltage, v ddl , of the internal logic circuit, program memory, ram, low-speed oscillation, etc. 23.1.2 configuration figure 23-1 shows the configuration of the power supply circuit. figure 23-1 configuration of power supply circuit 23.1.3 list of pins pin name i/o function v ddl ? positive power supply pin for the internal logic circuits the v ddl voltage becomes approximately 1. 2 v at a system reset. at a system reset, the oscillation fr equency of the high-speed oscillation circuit (cr oscillator circuit) is set to 500khz. when the oscillation frequency of the high-speed oscillator ci rcuit (cr oscillation circuit) is set to 2mhz, the v ddl voltage becomes approximately 1.5v. v dd v ss v dd = 1.25 to 3.6v (when hsclk set to 500khz) 1.80 to 3.6v ( when hsclk set to 2mhz ) v ddl voltage regulator circuit for logic vrl low-speed oscillation circuit logic circuit high-speed oscillation circuit (cr oscillator circuit) port gpio xt0 xt1 general-purpose port cl
chapter 24 on-chip debug
ml610q407/ml610q408/ml610q409 user's manual chapter 24 on-chip debug 24-1 24. on-chip debug function 24.1 overview this lsi has an on-chip debug functi on allowing flash memory rewriting. the on-chip debug emulator (uease) is connected to this lsi to perform the on-chip debug function. this function is included only in the ml610q407 to 409 and not in the ml610407 to 409. 24.2 method of connecting to on-chip debug emulator figure 24-1 shows connection to the on-chip debug emulator (uease). for on-chip debug emulator, see ?uease user?s manual?. figure 24-1 connection to on-chip debug emulator (uease) note: ?please do not apply lsis being used for debugging to mass production. ?when using the on-chip debug function or the flash rewrite function after mounting of the board, design the board so that the 6 pins (v pp , v ddl , v dd , v ss , test0, and test1_n) required for connection to the on-chip debug emulator can be connected. ??3.0v to 3.6v? has to be supplied to v dd while debugging and writing flash. for details, see ?uease user?s manual? and ?uease target connection manual?. v pp ml610q407/8/9 test1_n test0 v dd v ss uease reset_n test v dd v ss user application circuit interface connector v pp v ddl v ddl
ml610q407/ml610q408/ml610q409 user's manual chapter 24 on-chip debug 24-2 24.3 flash memory rewrite function flash memory erase/write can be performed with the memory mounted on board by using the commands from the on-chip debug emulator (uease). for more details on th e on-chip debug emulator, see ?uease user?s manual?. table 24-2 shows the flash memory rewrite functions. table 24-2 flash memory rewrite functions function outline chip erase erase of 16 kwords (overall area) block erase erase of 2 kwords (4 kbytes) 1-word write write of 1 word (2 bytes) random read read of input address table 24-3 shows the conditions and specifications of flash memory rewrite. table 24-3 specifications of flash memory rewrite parameter specifications rewrite count 80cycles operating temperature 0c to 40c v pp 8 v (typ.) (supplied from uease) v dd 3.0v to 3.6v operating voltage v ddl 1.5 v/2.7 v (typ.) (supplied from uease) chip-erase time (typ.) 77ms (max.) 100ms block-erase time (typ.) 77ms (max.) 100ms 1-word (16 bits) write (typ.) 41 s (max.) 64 s overall-word (16k x 16 bits) write appr ox. 0.68s (typ.) approx. 1.05s (max.) note: when performing flash memory rewrite (erase, write), a vo ltage within the range from 3.0v to 3.6 v needs to be applied to the power supply voltage v dd .
chapter 25 mask rom version emulation function
ml610q407/ml610q408/ml610q 409 user?s manual chapter 25 mask type emulation function 25-1 25. mask rom version emulation function 25.1 overview mtp version (ml610q407/ml610q407/ml610q409) has mask rom version emulation function for mask rom version (ml610401/ ml610402/ ml610403/ml610404/ml610405/ml610406/ml610407/ml610408/ml610409) software program development. table 25-1 shows mtp vers ion selection for the so ftware program development in each mask type. table 25-1 mtp version selection for the software program development in each mask rom version mask rom version mtp version used for program development ml610401 ml610402 ml610403 ml610404 ml610405 ml610406 ml610407 ml610q407 ml610408 ml610q408 ml610409 ml610q409 mask rom version emulation function will be available once each mask rom version se tting data is written in the test region of the program memory. the program which is developed by this mask rom version emulation function can be directory entered to mask rom version mass production. 25.2 mask rom version mode setting sequence the blank product of mtp version ml 610q407/ml610q408/ml610q409 starts up in each ml610407/ml610408/ml610409 mode in th e ex-factory condition. when using mtp version ml610q407 for mask rom version ml610401/ml610402/ml610403/ml610404/ml610405/ ml610406 program development, each mask rom version setting must be done by the steps show n below. the steps explain an example of ml610401 mode se tting on ml610q407 reference board. 1) connect ml610q407 reference board and the uease. (*1) 2) connect uease and pc with usb cable. 3) boot fwuease flash writer host program ?fwuease flash writer? on the microsoft windows. 4) select ?ml610q407? in the ?target? field. 5) assign ml610401 mask rom versi on setting file named ?mode610401.hex? (*2) in ?file name? field of ?flash memory write/verify? group. 6) click ?add to list? button and enter it to the file list. 7) click ?write? button and write it on the flash memory. 8) click ?exit? button and exit the fwuease flash writer host program. 9) disconnect uease from pc. ml610401 m ode setting is completed. after re -boot the reference board, uease recognizes ml601q407 reference board as ml610401. sel ect ?ml610401? in the ?select target? window of fwuease flash writer host program ?fwuease flash writer?. and select ?ml610401? in the ?target chip? field of dtu8 debugger simulator ?dtu8 debugger?. (*1) the uease firmware version 1.12 or upper vers ion must be used for ml610q407/ml610q 408/ml610q409. please check uease firmware version before starting. fo r the uease firmware version, check ?help?->?system information? menu on dtu8. (*2) mask rom version setting file is prepared for each ml61040x mask rom version product in u8devhex folder as mode61040x.hex.
ml610q407/ml610q408/ml610q 409 user?s manual chapter 25 mask type emulation function 25-2 25.3 notice for the software program development 25.3.1 notice for the mask rom version mode setting data when developing mask rom version (ml610401/ml610402/ml610403/ml610404/ml610405/ml610406) program with mtp version ml610q407, mask rom version mode data must be set in the test region of the program memory. if the startup file is not used, put unused address region and test region program shown below into the program. put these unused address region and test region program into th e program of mtp version(ml610q407/ml610q408/ml610q409) and mask rom version(ml610407/ml610408/ml610409), too. z unused address region and test region program for ml610401 (low speed clock stop detection reset enable setting) ;--------------------------------------------------------------- ; filling the extra area at code memory (for ml610q401) ;--------------------------------------------------------------- cseg at 01700h dw 1280h dup 0ffffh ;--------------------------------------------------------------- ; filling the test area at code memory (for ml610q401) ;--------------------------------------------------------------- cseg at 03c00h dw 0f4h dup 0ffffh cseg at 03de8h dw 04010h ;target configuration data 1 dw 02b48h ;target configuration data 2 dw 000f0h ;target configuration data 3 dw 0a55ah ;target configuration data 4 cseg at 03df0h dw 8h dup 0ffffh ; ;--------------------------------------------------------------- ; keeping the mirror area (for ml610q401) ;--------------------------------------------------------------- tseg #8 at 00000h ds 03e00h
ml610q407/ml610q408/ml610q 409 user?s manual chapter 25 mask type emulation function 25-3 z unused address region and test region program for ml610402 (low speed clock stop detection reset enable setting) ;--------------------------------------------------------------- ; filling the extra area at code memory (for ml610q402) ;--------------------------------------------------------------- cseg at 01700h dw 1280h dup 0ffffh ;--------------------------------------------------------------- ; filling the test area at code memory (for ml610q402) ;--------------------------------------------------------------- cseg at 03c00h dw 0f4h dup 0ffffh cseg at 03de8h dw 04020h ;target configuration data 1 dw 02948h ;target configuration data 2 dw 000f0h ;target configuration data 3 dw 0a55ah ;target configuration data 4 cseg at 03df0h dw 8h dup 0ffffh ; ;--------------------------------------------------------------- ; keeping the mirror area (for ml610q402) ;--------------------------------------------------------------- tseg #8 at 00000h ds 03e00h z unused address region and test region program for ml610403 (low speed clock stop detection reset enable setting) ;--------------------------------------------------------------- ; filling the extra area at code memory (for ml610q403) ;--------------------------------------------------------------- cseg at 01700h dw 1280h dup 0ffffh ;--------------------------------------------------------------- ; filling the test area at code memory (for ml610q403) ;--------------------------------------------------------------- cseg at 03c00h dw 0f4h dup 0ffffh cseg at 03de8h dw 04030h ;target configuration data 1 dw 02848h ;target configuration data 2 dw 000f0h ;target configuration data 3 dw 0a55ah ;target configuration data 4 cseg at 03df0h dw 8h dup 0ffffh ; ;--------------------------------------------------------------- ; keeping the mirror area (for ml610q403) ;--------------------------------------------------------------- tseg #8 at 00000h ds 03e00h
ml610q407/ml610q408/ml610q 409 user?s manual chapter 25 mask type emulation function 25-4 z unused address region and test region program for ml610404 (low speed clock stop detection reset enable setting) ;--------------------------------------------------------------- ; filling the extra area at code memory (for ml610q404) ;--------------------------------------------------------------- cseg at 01f00h dw 0e80h dup 0ffffh ;--------------------------------------------------------------- ; filling the test area at code memory (for ml610q404) ;--------------------------------------------------------------- cseg at 03c00h dw 0f4h dup 0ffffh cseg at 03de8h dw 04040h ;target configuration data 1 dw 06fffh ;target configuration data 2 dw 000f5h ;target configuration data 3 dw 0a55ah ;target configuration data 4 cseg at 03df0h dw 8h dup 0ffffh ; ;--------------------------------------------------------------- ; keeping the mirror area (for ml610q404) ;--------------------------------------------------------------- tseg #8 at 00000h ds 03e00h z unused address region and test region program for ml610405 (low speed clock stop detection reset enable setting) ;--------------------------------------------------------------- ; filling the extra area at code memory (for ml610q405) ;--------------------------------------------------------------- cseg at 01f00h dw 0e80h dup 0ffffh ;--------------------------------------------------------------- ; filling the test area at code memory (for ml610q405) ;--------------------------------------------------------------- cseg at 03c00h dw 0f4h dup 0ffffh cseg at 03de8h dw 04050h ;target configuration data 1 dw 06dffh ;target configuration data 2 dw 000f5h ;target configuration data 3 dw 0a55ah ;target configuration data 4 cseg at 03df0h dw 8h dup 0ffffh ; ;--------------------------------------------------------------- ; keeping the mirror area (for ml610q405) ;--------------------------------------------------------------- tseg #8 at 00000h ds 03e00h
ml610q407/ml610q408/ml610q 409 user?s manual chapter 25 mask type emulation function 25-5 z unused address region and test region program for ml610406 (low speed clock stop detection reset enable setting) ;--------------------------------------------------------------- ; filling the extra area at code memory (for ml610q406) ;--------------------------------------------------------------- cseg at 01f00h dw 0e80h dup 0ffffh ;--------------------------------------------------------------- ; filling the test area at code memory (for ml610q406) ;--------------------------------------------------------------- cseg at 03c00h dw 0f4h dup 0ffffh cseg at 03de8h dw 04060h ;target configuration data 1 dw 06cffh ;target configuration data 2 dw 000f5h ;target configuration data 3 dw 0a55ah ;target configuration data 4 cseg at 03df0h dw 8h dup 0ffffh ; ;--------------------------------------------------------------- ; keeping the mirror area (for ml610q406) ;--------------------------------------------------------------- tseg #8 at 00000h ds 03e00h z unused address region and test region program for ml610407/408/409 and ml610q407/q408/q409 (low speed clock stop detection reset enable setting) ;--------------------------------------------------------------- ; filling the test area at code memory (for ml610407/8/9/q407/8/9) ;--------------------------------------------------------------- cseg at 03c00h dw 100h dup 0ffffh ;--------------------------------------------------------------- ; keeping the mirror area (for ml610407/8/9/q407/8/9) ;--------------------------------------------------------------- tseg #8 at 00000h ds 03e00h
ml610q407/ml610q408/ml610q 409 user?s manual chapter 25 mask type emulation function 25-6 z unused address region and test region program for ml610401 (low speed clock stop detection reset disable setting) ;--------------------------------------------------------------- ; filling the extra area at code memory (for ml610q401) ;--------------------------------------------------------------- cseg at 01700h dw 1280h dup 0ffffh ;--------------------------------------------------------------- ; filling the test area at code memory (for ml610q401) ;--------------------------------------------------------------- cseg at 03c00h dw 0f4h dup 0ffffh cseg at 03de8h dw 04010h ;target configuration data 1 dw 02348h ;target configuration data 2 dw 000f0h ;target configuration data 3 dw 0a55ah ;target configuration data 4 cseg at 03df0h dw 8h dup 0ffffh ; ;--------------------------------------------------------------- ; keeping the mirror area (for ml610q401) ;--------------------------------------------------------------- tseg #8 at 00000h ds 03e00h z unused address region and test region program for ml610402 (low speed clock stop detection reset disable setting) ;--------------------------------------------------------------- ; filling the extra area at code memory (for ml610q402) ;--------------------------------------------------------------- cseg at 01700h dw 1280h dup 0ffffh ;--------------------------------------------------------------- ; filling the test area at code memory (for ml610q402) ;--------------------------------------------------------------- cseg at 03c00h dw 0f4h dup 0ffffh cseg at 03de8h dw 04020h ;target configuration data 1 dw 02148h ;target configuration data 2 dw 000f0h ;target configuration data 3 dw 0a55ah ;target configuration data 4 cseg at 03df0h dw 8h dup 0ffffh ; ;--------------------------------------------------------------- ; keeping the mirror area (for ml610q402) ;--------------------------------------------------------------- tseg #8 at 00000h ds 03e00h
ml610q407/ml610q408/ml610q 409 user?s manual chapter 25 mask type emulation function 25-7 z unused address region and test region program for ml610403 (low speed clock stop detection reset disable setting) ;--------------------------------------------------------------- ; filling the extra area at code memory (for ml610q403) ;--------------------------------------------------------------- cseg at 01700h dw 1280h dup 0ffffh ;--------------------------------------------------------------- ; filling the test area at code memory (for ml610q403) ;--------------------------------------------------------------- cseg at 03c00h dw 0f4h dup 0ffffh cseg at 03de8h dw 04030h ;target configuration data 1 dw 02048h ;target configuration data 2 dw 000f0h ;target configuration data 3 dw 0a55ah ;target configuration data 4 cseg at 03df0h dw 8h dup 0ffffh ; ;--------------------------------------------------------------- ; keeping the mirror area (for ml610q403) ;--------------------------------------------------------------- tseg #8 at 00000h ds 03e00h z unused address region and test region program for ml610404 (low speed clock stop detection reset disable setting) ;--------------------------------------------------------------- ; filling the extra area at code memory (for ml610q404) ;--------------------------------------------------------------- cseg at 01f00h dw 0e80h dup 0ffffh ;--------------------------------------------------------------- ; filling the test area at code memory (for ml610q404) ;--------------------------------------------------------------- cseg at 03c00h dw 0f4h dup 0ffffh cseg at 03de8h dw 04040h ;target configuration data 1 dw 067ffh ;target configuration data 2 dw 000f5h ;target configuration data 3 dw 0a55ah ;target configuration data 4 cseg at 03df0h dw 8h dup 0ffffh ; ;--------------------------------------------------------------- ; keeping the mirror area (for ml610q404) ;--------------------------------------------------------------- tseg #8 at 00000h ds 03e00h
ml610q407/ml610q408/ml610q 409 user?s manual chapter 25 mask type emulation function 25-8 z unused address region and test region program for ml610405 (low speed clock stop detection reset disable setting) ;--------------------------------------------------------------- ; filling the extra area at code memory (for ml610q405) ;--------------------------------------------------------------- cseg at 01f00h dw 0e80h dup 0ffffh ;--------------------------------------------------------------- ; filling the test area at code memory (for ml610q405) ;--------------------------------------------------------------- cseg at 03c00h dw 0f4h dup 0ffffh cseg at 03de8h dw 04050h ;target configuration data 1 dw 065ffh ;target configuration data 2 dw 000f5h ;target configuration data 3 dw 0a55ah ;target configuration data 4 cseg at 03df0h dw 8h dup 0ffffh ; ;--------------------------------------------------------------- ; keeping the mirror area (for ml610q405) ;--------------------------------------------------------------- tseg #8 at 00000h ds 03e00h z unused address region and test region program for ml610406 (low speed clock stop detection reset disable setting) ;--------------------------------------------------------------- ; filling the extra area at code memory (for ml610q406) ;--------------------------------------------------------------- cseg at 01f00h dw 0e80h dup 0ffffh ;--------------------------------------------------------------- ; filling the test area at code memory (for ml610q406) ;--------------------------------------------------------------- cseg at 03c00h dw 0f4h dup 0ffffh cseg at 03de8h dw 04060h ;target configuration data 1 dw 064ffh ;target configuration data 2 dw 000f5h ;target configuration data 3 dw 0a55ah ;target configuration data 4 cseg at 03df0h dw 8h dup 0ffffh ; ;--------------------------------------------------------------- ; keeping the mirror area (for ml610q406) ;--------------------------------------------------------------- tseg #8 at 00000h ds 03e00h
ml610q407/ml610q408/ml610q 409 user?s manual chapter 25 mask type emulation function 25-9 z unused address region and test region program for ml610407/408/409 (low speed clock stop detection reset disable setting) ;--------------------------------------------------------------- ; filling the test area at code memory (for ml610407/8/9/q407/8/9) cseg at 03c00h dw 0f4h dup 0ffffh cseg at 03de8h dw 0ffffh ;target configuration data 1 dw 0f7ffh ;target configuration data 2 dw 0ffffh ;target configuration data 3 dw 0ffffh ;target configuration data 4 ;--------------------------------------------------------------- ; keeping the mirror area (for ml610407/8/9/q407/8/9) ;--------------------------------------------------------------- tseg #8 at 00000h ds 03e00h
ml610q407/ml610q408/ml610q 409 user?s manual chapter 25 mask type emulation function 25-10 25.3.2 notice for the mask rom version mode memory size the mtp version (ml610q407) rom size is 16kb. even if mask version mode is set on mtp version, rom size itself is 16kb physically. therefore, do not put the progr am code on the unusable address region fo r each mask version mode. please always use the startup file when the program is developed by c la nguage, because the usable addre ss region for each mask version mode is defined on the startup file. usable/unusable region for the program on the flash memory address in each mask version mode is shown below. address 401/402/403 mode address 404/405/406 mode address 407/408/409 mode 00000h 016ffh usable address region for the program 5,888byte except 256byte test region 00000h 03defh usable address region for the program 7,936byte except 256byte test region 00000h 03bffh usable address region for the program 15,360byte except 1024 byte test region 01700h 03fffh unusable address region for the program (*) 03df0h 03fffh unusable address region for the program (*) 03c00h 03fffh unusable address region for the program (*) usable/unusable region for the program on the fl ash memory address in each mask version mode (*) on unusable address regison for the program, please defi ne the mask rom version mode setting data shown in the section25.3.1, and please define ?ffh? on the unused region. in case the start file is used for the programming, if the progr am code is put on the unusable address region, the warinig show n below is issued when the program is compiled. warning w011: code/table segments overlap
ml610q407/ml610q408/ml610q 409 user?s manual chapter 25 mask type emulation function 25-11 25.4 the detail specification of mask rom version mode table 25-2 shows ml610q407 mask rom version mode function list by ml610q407. table 25-2 (1/4) mask rom version mode function list by ml610q407 mask rom version mode mask rom version mode /product 401 402 403 404 405 406 ml610q407 rom 16kb (*1) 16kb (*2) 16kb(mtp) ram 192b 256b 1kb lcd driver (*3) segment (max.dot) 2c-14s 3c-13s 4c-12s 5c-11s (55) 2c-18s 3c-17s 4c-16s 5c-15s (75) 2c-22s 3c-21s 4c-20s 5c-19s (95) 2c-24s 3c-23s 4c-22s 5c-21s (105) 2c-28s 3c-27s 4c-26s 5c-25s (120) 2c-32s 3c-31s 4c-30s 5c-29s (145) 2c-32s 3c-31s 4c-30s 5c-29s (145) input (*4) 4 5 5 output (*5) 12 8 4 12 8 4 12 ports i/o (*6) 18 22 22 a/d converter 16bit rc type x2 serial i/f (* ) uart x 1 ssio(spi) x 2 uart x 1 timer (*8) 8bit-timer x 2 8bit timer x 4 pwm (*9) - 16bit-pwm x 1 timers others tbc(time base counte r) x 1, wdt x 1, capture x 2 ext. interrupt (*10) 8 (incl. 4bit-or) 13 (incl. 8bit-or) buzzer/melody buzzer/melody other function low-speed clock frequency adjustment, clock out high (*11) 500khz (internal rc) 500khz/2mhz (internal rc) operating frequency low 32.768khz(crystal oscilation) (*1) the rom size of mask rom version ml610401/402/403 is 6kb. please define ffh in unused address region in the program. (*2) the rom size of mask rom version ml610404/405/406 is 8kb. please define ffh in unused address region in the program. (*3) usable segment pins in each mask rom version mode can be seen in the 25-2 (4/4). unusable segment pins in each mask rom version mode output off waveform. (*4) for 401, 402 and 403 mode, p04 can not be used. please fix it to v ss . (*5) for 403 and 406 mode, port6 function can not be used. because po rt6 (p60 to p67) pins become hi-z output in this mode, please make these pins to be open. for 402 and 405 mode, p64 to p67 can not be used. because p64 to p67 pins become hi-z output in this mode, please make these pins to be open. (*6) for 401, 402, and 403 mode, p54 to p57 pins can not be used. b ecause p54 to p57 pins become hi-z output in this mode, please make these pins to be open. (*7) for 401, 402, and 403 mode, synchronous serial port: ssio0 and ssio1 can not be used. (*8) for 401, 402, and 403 mode, timer0 and timer1 can not be used. (*9) for 401, 402, and 403 mode, pwm can not be used. (*10) for 401, 402, and 403 mode, p04 and p54 to p57 pins can not be used. the pins for the extern al interrupt are p00, p01, p02,p03, and p50 to p53 in this mode. (*11) for 401, 402, and 403 mode, internal rc oscillation is limite d to 500khz. 2mhz oscillation can not be used. and v ddl is always typ. 1.2v for this mode.
ml610q407/ml610q408/ml610q 409 user?s manual chapter 25 mask type emulation function 25-12 table 25-2 (2/4) mask rom version mode function table by ml610q407 : usable ? : partial function avairable : unusable ml610q407 primary/secondary/tertiary function mask rom version mode primary function secondary/tertiary function pin name i/o function secondary /tertiary pin name i/o function 401/402/403 mode 404/405/406 mode vss ? negative power supply pin ? ? ? ? v dd ? positive power supply pin ? ? ? ? v ddl ? power supply pin for internal logic (internally generated) ? ? ? ? v pp ? power supply pin for flash rom ? ? ? ? v l1 ? power supply pin for lcd bias (internally generated or connected to positive power supply pin) (*2) ? ? ? ? v l2 ? power supply pin for lcd bias (internally generated or connected to positive power supply pin) (*2) ? ? ? ? v l3 ? power supply pin for lcd bias (internally generated) ? ? ? ? c1 ? capacitor connection pin for lcd bias generation ? ? ? ? c2 ? capacitor connection pin for lcd bias generation ? ? ? ? test0 i/o test pin ? ? ? ? test1_n i test pin ? ? ? ? reset_n i reset input pin ? ? ? ? xt0 i low-speed clock oscillation pin ? ? ? ? xt1 o low-speed clock oscillation pin ? ? ? ? p00/exi0/ cap0 i input port, external interrupt, capture 0 input ? ? ? ? p01/exi1/ cap1 i input port, external interrupt, capture 1 input ? ? ? ? p02/exi2/ rxd0 i input port, external interrupt, uart0 received data ? ? ? ? p03/exi3 i input port, external interrupt ? ? ? ? p04 /exi4/ t02p0ck i input port, timer 0/timer 2/pwm0 external clock input external interrupt ? ? ? ? (?1) p20/led0 o output port secondary lsclk o low-speed clock output p21/led1 o output port secondary outclk o high-speed clock output p22/led2 o output port secondary md0 o melody 0 output p24/led4 o output port secondary pwm0 o pwm0 output (?2) p30 i/o input/output port secondary in0 i rc type adc0 oscillation input pin p31 i/o input/output port secondary cs0 o rc type adc0 reference capacitor connection pin p34 i/o input/output port secondary rct0 o rc type adc0 resistor/capacitor sensor connection pin p32 i/o input/output port secondary rs0 o rc type adc0 reference resistor connection pin p33 i/o input/output port secondary rt0 o rc type adc0 measurement resistor sensor connection pin p35 i/o input/output port secondary rcm o rc type adc oscillation monitor (*1) for 401, 402 and 403 mode, p04 can not be used. please fix it to vss. (*2) for 401, 402 and 403 mode, secondary function : pwm0 can not be used.
ml610q407/ml610q408/ml610q 409 user?s manual chapter 25 mask type emulation function 25-13 table 25-2 (3/4) mask rom version mode function table by ml610q407 : usable ? : partial function avairable : unusable ml610q407 primary/secondary/tertiary function mask rom version mode primary function secondary/tertiary function pin name i/o function secondar y/tertiary pin name i/o function 401/402/403 mode 404/405/406 mode secondary ? ? ? p40 i/o input/output port tertiary sin0 i ssio0 data input (?1) secondary ? ? ? p41 i/o input/output port tertiary sck0 i/o ssio0 synchronous clock input/output (?1) secondary rxd0 i uart data input p42 i/o input/output port tertiary sout0 o ssio0 data output (?1) secondary txd0 o uart data output p43 i/o input/output port tertiary pwm0 o pwm0 output (?2) secondary in1 i rc type adc1 oscillation input pin p44/ t02p0ck i/o input/output port, timer 0/timer 2/pwm0 external clock input tertiary sin0 i ssio0 data input (?1) secondary cs1 o rc type adc1 reference capacitor connection pin p45/ t13ck i/o input/output port, timer 1/timer 3 external clock input tertiary sck0 i/o ssio0 synchronous clock input/output (?1) secondary rs1 o rc type adc1 reference resistor connection pin p46 i/o input/output port tertiary sout0 o ssio0 data output (?1) p47 i/o input/output port secondary rt1 o rc type adc1 measurement resistor sensor connection pin secondary md0 o melody 0 output p50/exi8 i/o input/output port, external interrupt tertiary sin1 i ssio1 data input (?3) secondary ? ? ? p51/exi8 i/o input/output port, external interrupt tertiary sck1 i/o ssio1 synchronous clock input/output (?3) secondary ? ? ? p52/exi8 i/o input/output port, external interrupt tertiary sout1 o ssio1 data output (?3) p53/exi8 i/o input/output port, external interrupt ? ? ? ? secondary ? ? ? p54/exi8 i/o input/output port, external interrupt tertiary sin1 i ssio1 data input (?4) secondary ? ? ? p55/exi8 i/o input/output port, external interrupt tertiary sck1 i/o ssio1 synchronous clock input/output (?4) secondary ? ? ? p56/exi8 i/o input/output port, external interrupt tertiary sout1 o ssio1 data output (?4) p57/exi8 i/o input/output port, external interrupt ? ? ? ? (?4) (*1) for 401, 402, and 403 mode, tertiary function : ssio0 can not be used. (*2) for 401, 402, and 403 mode, tertiary function : pwm0 can not be used. (*3) for 401, 402, and 403 mode, tertiary function : ssio1 can not be used. (*4) for 401, 402, and 403 mode, p54 to p57 can not be used. please make p54 to p57 pin to be open.
ml610q407/ml610q408/ml610q 409 user?s manual chapter 25 mask type emulation function 25-14 table 25-2 (4/4) mask rom version mode function table by ml610q407 : usable ? : partial function avairable : unusable ml610q407 primary/secondary/tertiary function mask rom version mode pin name i/o primary function 401 mode 402 mode 403 mode 404 mode 405 mode 406 mode com0 o lcd common pin com1 o lcd common pin com2/seg0 o lcd common/segment pin com3/seg1 o lcd common/segment pin com4/seg2 o lcd common/segment pin seg3 o lcd segment pin seg4 o lcd segment pin seg5 o lcd segment pin seg6 o lcd segment pin seg7 o lcd segment pin seg8 o lcd segment pin seg9 o lcd segment pin seg10 o lcd segment pin seg11 o lcd segment pin seg12 o lcd segment pin seg13 o lcd segment pin seg14 o lcd segment pin (?1) seg15 o lcd segment pin (?1) seg16 o lcd segment pin (?1) seg17 o lcd segment pin (?1) seg18 o lcd segment pin (?1) (?2) seg19 o lcd segment pin (?1) (?2) seg20 o lcd segment pin (?1) (?2) seg21 o lcd segment pin (?1) (?2) seg22 o lcd segment pin (?1) (?2) (?3) seg23 o lcd segment pin (?1) (?2) (?3) seg24 o lcd segment pin (?1) (?2) (?3) (?4) seg25 o lcd segment pin (?1) (?2) (?3) (?4) seg26 o lcd segment pin (?1) (?2) (?3) (?4) seg27 o lcd segment pin (?1) (?2) (?3) (?4) seg28 o lcd segment pin (?1) (?2) (?3) (?4) (?5) seg29 o lcd segment pin (?1) (?2) (?3) (?4) (?5) seg30 o lcd segment pin (?1) (?2) (?3) (?4) (?5) seg31 o lcd segment pin (?1) (?2) (?3) (?4) (?5) p67 o output port (?6) (?7) (?6) (?7) p66 o output port (?6) (?7) (?6) (?7) p65 o output port (?6) (?7) (?6) (?7) p64 o output port (?6) (?7) (?6) (?7) p63 o output port (?7) (?7) p62 o output port (?7) (?7) p61 o output port (?7) (?7) p60 o output port (?7) (?7) (*1) for 401 mode, seg14 to seg39 can not be used. (*2) for 402 mode, seg18 to seg39 can not be used. (*3) for 403 mode, seg22 to seg39 can not be used. (*4) for 404 mode, seg24 to seg39 can not be used. (*5) for 405 mode, seg24 to seg39 can not be used. (*6) for 402 and 405 mode, p64 to p67 can not be used . please make p64 to p67 pin to be open. (*7) for 403 and 406 mode, p60 to p67 can not be used . please make p60 to p67 pin to be open.
ml610q407/ml610q408/ml610q 409 user?s manual chapter 25 mask type emulation function 25-12 table 25-2 (2/4) mask rom version mode function table by ml610q407 : usable ? : partial function avairable : unusable ml610q407 primary/secondary/tertiary function mask rom version mode primary function secondary/tertiary function pin name i/o function secondary /tertiary pin name i/o function 401/402/403 mode 404/405/406 mode vss ? negative power supply pin ? ? ? ? v dd ? positive power supply pin ? ? ? ? v ddl ? power supply pin for internal logic (internally generated) ? ? ? ? v pp ? power supply pin for flash rom ? ? ? ? v l1 ? power supply pin for lcd bias (internally generated or connected to positive power supply pin) (*2) ? ? ? ? v l2 ? power supply pin for lcd bias (internally generated or connected to positive power supply pin) (*2) ? ? ? ? v l3 ? power supply pin for lcd bias (internally generated) ? ? ? ? c1 ? capacitor connection pin for lcd bias generation ? ? ? ? c2 ? capacitor connection pin for lcd bias generation ? ? ? ? test0 i/o test pin ? ? ? ? test1_n i test pin ? ? ? ? reset_n i reset input pin ? ? ? ? xt0 i low-speed clock oscillation pin ? ? ? ? xt1 o low-speed clock oscillation pin ? ? ? ? p00/exi0/ cap0 i input port, external interrupt, capture 0 input ? ? ? ? p01/exi1/ cap1 i input port, external interrupt, capture 1 input ? ? ? ? p02/exi2/ rxd0 i input port, external interrupt, uart0 received data ? ? ? ? p03/exi3 i input port, external interrupt ? ? ? ? p04 /exi4/ t02p0ck i input port, timer 0/timer 2/pwm0 external clock input external interrupt ? ? ? ? (?1) p20/led0 o output port secondary lsclk o low-speed clock output p21/led1 o output port secondary outclk o high-speed clock output p22/led2 o output port secondary md0 o melody 0 output p24/led4 o output port secondary pwm0 o pwm0 output (?2) p30 i/o input/output port secondary in0 i rc type adc0 oscillation input pin p31 i/o input/output port secondary cs0 o rc type adc0 reference capacitor connection pin p34 i/o input/output port secondary rct0 o rc type adc0 resistor/capacitor sensor connection pin p32 i/o input/output port secondary rs0 o rc type adc0 reference resistor connection pin p33 i/o input/output port secondary rt0 o rc type adc0 measurement resistor sensor connection pin p35 i/o input/output port secondary rcm o rc type adc oscillation monitor (*1) for 401, 402 and 403 mode, p04 can not be used. please fix it to vss. (*2) for 401, 402 and 403 mode, secondary function : pwm0 can not be used.
ml610q407/ml610q408/ml610q 409 user?s manual chapter 25 mask type emulation function 25-13 table 25-2 (3/4) mask rom version mode function table by ml610q407 : usable ? : partial function avairable : unusable ml610q407 primary/secondary/tertiary function mask rom version mode primary function secondary/tertiary function pin name i/o function secondar y/tertiary pin name i/o function 401/402/403 mode 404/405/406 mode secondary ? ? ? p40 i/o input/output port tertiary sin0 i ssio0 data input (?1) secondary ? ? ? p41 i/o input/output port tertiary sck0 i/o ssio0 synchronous clock input/output (?1) secondary rxd0 i uart data input p42 i/o input/output port tertiary sout0 o ssio0 data output (?1) secondary txd0 o uart data output p43 i/o input/output port tertiary pwm0 o pwm0 output (?2) secondary in1 i rc type adc1 oscillation input pin p44/ t02p0ck i/o input/output port, timer 0/timer 2/pwm0 external clock input tertiary sin0 i ssio0 data input (?1) secondary cs1 o rc type adc1 reference capacitor connection pin p45/ t13ck i/o input/output port, timer 1/timer 3 external clock input tertiary sck0 i/o ssio0 synchronous clock input/output (?1) secondary rs1 o rc type adc1 reference resistor connection pin p46 i/o input/output port tertiary sout0 o ssio0 data output (?1) p47 i/o input/output port secondary rt1 o rc type adc1 measurement resistor sensor connection pin secondary md0 o melody 0 output p50/exi8 i/o input/output port, external interrupt tertiary sin1 i ssio1 data input (?3) secondary ? ? ? p51/exi8 i/o input/output port, external interrupt tertiary sck1 i/o ssio1 synchronous clock input/output (?3) secondary ? ? ? p52/exi8 i/o input/output port, external interrupt tertiary sout1 o ssio1 data output (?3) p53/exi8 i/o input/output port, external interrupt ? ? ? ? secondary ? ? ? p54/exi8 i/o input/output port, external interrupt tertiary sin1 i ssio1 data input (?4) secondary ? ? ? p55/exi8 i/o input/output port, external interrupt tertiary sck1 i/o ssio1 synchronous clock input/output (?4) secondary ? ? ? p56/exi8 i/o input/output port, external interrupt tertiary sout1 o ssio1 data output (?4) p57/exi8 i/o input/output port, external interrupt ? ? ? ? (?4) (*1) for 401, 402, and 403 mode, tertiary function : ssio0 can not be used. (*2) for 401, 402, and 403 mode, tertiary function : pwm0 can not be used. (*3) for 401, 402, and 403 mode, tertiary function : ssio1 can not be used. (*4) for 401, 402, and 403 mode, p54 to p57 can not be used. please make p54 to p57 pin to be open.
ml610q407/ml610q408/ml610q 409 user?s manual chapter 25 mask type emulation function 25-14 table 25-2 (4/4) mask rom version mode function table by ml610q407 : usable ? : partial function avairable : unusable ml610q407 primary/secondary/tertiary function mask rom version mode pin name i/o primary function 401 mode 402 mode 403 mode 404 mode 405 mode 406 mode com0 o lcd common pin com1 o lcd common pin com2/seg0 o lcd common/segment pin com3/seg1 o lcd common/segment pin com4/seg2 o lcd common/segment pin seg3 o lcd segment pin seg4 o lcd segment pin seg5 o lcd segment pin seg6 o lcd segment pin seg7 o lcd segment pin seg8 o lcd segment pin seg9 o lcd segment pin seg10 o lcd segment pin seg11 o lcd segment pin seg12 o lcd segment pin seg13 o lcd segment pin seg14 o lcd segment pin (?1) seg15 o lcd segment pin (?1) seg16 o lcd segment pin (?1) seg17 o lcd segment pin (?1) seg18 o lcd segment pin (?1) (?2) seg19 o lcd segment pin (?1) (?2) seg20 o lcd segment pin (?1) (?2) seg21 o lcd segment pin (?1) (?2) seg22 o lcd segment pin (?1) (?2) (?3) seg23 o lcd segment pin (?1) (?2) (?3) seg24 o lcd segment pin (?1) (?2) (?3) (?4) seg25 o lcd segment pin (?1) (?2) (?3) (?4) seg26 o lcd segment pin (?1) (?2) (?3) (?4) seg27 o lcd segment pin (?1) (?2) (?3) (?4) seg28 o lcd segment pin (?1) (?2) (?3) (?4) (?5) seg29 o lcd segment pin (?1) (?2) (?3) (?4) (?5) seg30 o lcd segment pin (?1) (?2) (?3) (?4) (?5) seg31 o lcd segment pin (?1) (?2) (?3) (?4) (?5) p67 o output port (?6) (?7) (?6) (?7) p66 o output port (?6) (?7) (?6) (?7) p65 o output port (?6) (?7) (?6) (?7) p64 o output port (?6) (?7) (?6) (?7) p63 o output port (?7) (?7) p62 o output port (?7) (?7) p61 o output port (?7) (?7) p60 o output port (?7) (?7) (*1) for 401 mode, seg14 to seg39 can not be used. (*2) for 402 mode, seg18 to seg39 can not be used. (*3) for 403 mode, seg22 to seg39 can not be used. (*4) for 404 mode, seg24 to seg39 can not be used. (*5) for 405 mode, seg24 to seg39 can not be used. (*6) for 402 and 405 mode, p64 to p67 can not be used . please make p64 to p67 pin to be open. (*7) for 403 and 406 mode, p60 to p67 can not be used . please make p60 to p67 pin to be open.
appendixes
ml610q407/ml610q408/ml610q409 user's manual appendix a registers appendix a-1 appendix a registers address name symbol (byte) symbol (word) r/w size initial value 0f000h data segment register dsr ? r/w 8 00h 0f001h reset status register rstat ? r/w 8 undefined 0f002h frequency control register 0 fcon0 r/w 8/16 33h 0f003h frequency control register 1 fcon1 fcon r/w 8 00h 0f008h stop code acceptor stpacp ? w 8 undefined 0f009h standby control register sbycon ? w 8 00h 0f00ah low-speed time base counter register ltbr ? r/w 8 00h 0f00bh high-speed time base counter frequency divide register htbdr ? r/w 8 00h 0f00ch low-speed time base counter frequency adjustment register l ltbadjl r/w 8/16 00h 0f00dh low-speed time base counter frequency adjustment register h ltbadjh ltbadj r/w 8 00h 0f00eh watchdog timer control register wdtcon ? r/w 8 00h 0f00fh watchdog timer mode register wdtmod ? r/w 8 02h 0f011h interrupt enable register 1 ie1 ? r/w 8 00h 0f012h interrupt enable register 2 ie2 ? r/w 8 00h 0f013h interrupt enable register 3 ie3 ? r/w 8 00h 0f014h interrupt enable register 4 ie4 ? r/w 8 00h 0f015h interrupt enable register 5 ie5 ? r/w 8 00h 0f016h interrupt enable register 6 ie6 ? r/w 8 00h 0f017h interrupt enable register 7 ie7 ? r/w 8 00h 0f018h interrupt request register 0 irq0 ? r/w 8 00h 0f019h interrupt request register 1 irq1 ? r/w 8 00h 0f01ah interrupt request register 2 irq2 ? r/w 8 00h 0f01bh interrupt request register 3 irq3 ? r/w 8 00h 0f01ch interrupt request register 4 irq4 ? r/w 8 00h 0f01dh interrupt request register 5 irq5 ? r/w 8 00h 0f01eh interrupt request register 6 irq6 ? r/w 8 00h 0f01fh interrupt request register 7 irq7 ? r/w 8 00h 0f020h external interrupt cont rol register 0 exicon0 ? r/w 8 00h 0f021h external interrupt control register 1 exicon1 ? r/w 8 00h 0f022h external interrupt control r egister 2 exicon2 ? r/w 8 00h 0f028h block control register 0 blkcon0 ? r/w 8 00h 0f029h block control register 1 blkcon1 ? r/w 8 00h 0f02ah block control register 2 blkcon2 ? r/w 8 00h 0f02bh block control register 3 blkcon3 ? r/w 8 00h 0f02ch block control register 4 blkcon4 ? r/w 8 00h 0f030h timer 0 data register tm0d r/w 8/16 0ffh 0f031h timer 0 counter register tm0c tm0dc r/w 8 00h 0f032h timer 0 control register 0 tm0con0 r/w 8/16 00h 0f033h timer 0 control register 1 tm0con1 tm0con r/w 8 00h 0f034h timer 1 data register tm1d r/w 8/16 0ffh 0f035h timer 1 counter register tm1c tm1dc r/w 8 00h 0f036h timer 1 control register 0 tm1con0 tm1con r/w 8/16 00h
ml610q407/ml610q408/ml610q409 user's manual appendix a registers appendix a-2 address name symbol (byte) symbol (word) r/w size initial value 0f037h timer 1 control register 1 tm1con1 r/w 8 00h 0f038h timer 2 data register tm2d r/w 8/16 0ffh 0f039h timer 2 counter register tm2c tm2dc r/w 8 00h 0f03ah timer 2 control regist er 0 tm2con0 r/w 8/16 00h 0f03bh timer 2 control register 1 tm2con1 tm2con r/w 8 00h 0f03ch timer 3 data register tm3d r/w 8/16 0ffh 0f03dh timer 3 counter register tm3c tm3dc r/w 8 00h 0f03eh timer 3 control regist er 0 tm3con0 r/w 8/16 00h 0f03fh timer 3 control register 1 tm3con1 tm3con r/w 8 00h 0f090h capture control register capcon ? r/w 8 00h 0f091h capture status register capstat ? r/w 8 00h 0f092h capture data regi ster 0 capr0 ? r/w 8 00h 0f093h capture data regi ster 1 capr1 ? r/w 8 00h 0f094h capture time base data register captb ? r 8 undefined 0f0a0h pwm0 period register l pw0pl r/w 8/16 0ffh 0f0a1h pwm0 period register h pw0ph pw0p r/w 8 0ffh 0f0a2h pwm0 duty register l pw0dl r/w 8/16 00h 0f0a3h pwm0 duty register h pw0dh pw0d r/w 8 00h 0f0a4h pwm0 counter regi ster l pw0cl r/w 8/16 00h 0f0a5h pwm0 counter register h pw0ch pw0c r/w 8 00h 0f0a6h pwm0 control register 0 pw0con0 r/w 8/16 00h 0f0a7h pwm0 control register 1 pw0con1 pw0con r/w 8 40h 0f0f0h bias circuit control register biascon ? r/w 8 38h 0f0f2h display mode register 0 dspmod0 r/w 8/16 00h 0f0f3h display mode register 1 dspmod1 dspmod r/w 8 00h 0f0f4h display control register dspcon ? r/w 8 00h 0f100h display register 00 dspr00 ? r/w 8 undefined 0f101h display register 01 dspr01 ? r/w 8 undefined 0f102h display register 02 dspr02 ? r/w 8 undefined 0f103h display register 03 dspr03 ? r/w 8 undefined 0f104h display register 04 dspr04 ? r/w 8 undefined 0f105h display register 05 dspr05 ? r/w 8 undefined 0f106h display register 06 dspr06 ? r/w 8 undefined 0f107h display register 07 dspr07 ? r/w 8 undefined 0f108h display register 08 dspr08 ? r/w 8 undefined 0f109h display register 09 dspr09 ? r/w 8 undefined 0f10ah display register 0a dspr0a ? r/w 8 undefined 0f10bh display register 0b dspr0b ? r/w 8 undefined 0f10ch display register 0c dspr0c ? r/w 8 undefined 0f10dh display register 0d dspr0d ? r/w 8 undefined 0f10eh display register 0e dspr0e ? r/w 8 undefined 0f10fh display register 0f dspr0f ? r/w 8 undefined 0f110h display register 10 dspr10 ? r/w 8 undefined 0f111h display register 11 dspr11 ? r/w 8 undefined 0f112h display register 12 dspr12 ? r/w 8 undefined 0f113h display register 13 dspr13 ? r/w 8 undefined 0f114h display register 14 dspr14 ? r/w 8 undefined 0f115h display register 15 dspr15 ? r/w 8 undefined
ml610q407/ml610q408/ml610q409 user's manual appendix a registers appendix a-3 address name symbol (byte) symbol (word) r/w size initial value 0f116h display register 16 dspr16 ? r/w 8 undefined 0f117h display register 17 dspr17 ? r/w 8 undefined 0f118h display register 18 dspr18 ? r/w 8 undefined 0f119h display register 19 dspr19 ? r/w 8 undefined 0f11ah display register 1a dspr1a ? r/w 8 undefined 0f11bh display register 1b dspr1b ? r/w 8 undefined 0f11ch display register 1c dspr1c ? r/w 8 undefined 0f11dh display register 1d dspr1d ? r/w 8 undefined 0f11eh display register 1e dspr1e ? r/w 8 undefined 0f11fh display register 1f dspr1f ? r/w 8 undefined 0f120h display register 20 dspr20 ? r/w 8 undefined 0f121h display register 21 dspr21 ? r/w 8 undefined 0f122h display register 22 dspr22 ? r/w 8 undefined 0f123h display register 23 dspr23 ? r/w 8 undefined 0f124h display register 24 dspr24 ? r/w 8 undefined 0f125h display register 25 dspr25 ? r/w 8 undefined 0f126h display register 26 dspr26 ? r/w 8 undefined 0f127h display register 27 dspr27 ? r/w 8 undefined 0f204h port 0 data register p0d ? r 8 undefined 0f206h port 0 control register 0 p0con0 r/w 8/16 00h 0f207h port 0 control register 1 p0con1 p0con r/w 8 00h 0f210h port 2 data register p2d ? r/w 8 00h 0f212h port 2 control register 0 p2con0 r/w 8/16 00h 0f213h port 2 control register 1 p2con1 p2con r/w 8 00h 0f214h port 2 mode register p2mod ? r/w 8 00h 0f218h port 3 data register p3d ? r/w 8 00h 0f219h port 3 direction register p3dir ? r/w 8 00h 0f21ah port 3 control register 0 p3con0 r/w 8/16 00h 0f21bh port 3 control register 1 p3con1 p3con r/w 8 00h 0f21ch port 3 mode register 0 p3mod0 ? r/w 8 00h 0f220h port 4 data register p4d ? r/w 8 00h 0f221h port 4 direction register p4dir ? r/w 8 00h 0f222h port 4 control register 0 p4con0 r/w 8/16 00h 0f223h port 4 control register 1 p4con1 p4con r/w 8 00h 0f224h port 4 mode register 0 p4mod0 ? r/w 8 00h 0f225h port 4 mode register 1 p4mod1 ? r/w 8 00h 0f228h port 5 data register p5d ? r/w 8 ffh 0f229h port 5 direction register p5dir ? r/w 8 00h 0f22ah port 5 control register 0 p5con0 r/w 8/16 00h 0f22bh port 5 control register 1 p5con1 p5con r/w 8 00h 0f22ch port 5 mode register 0 p5mod0 ? r/w 8 00h 0f22dh port 5 mode register 1 p5mod1 ? r/w 8 00h 0f22eh port 5 interrupt mode register p5isel ? r/w 8 00h 0f230h port 6 data register (*1) p6d ? r/w 8 ffh (*2) 0fh (*3) 0f232h port 6 control register 0 (*1) p6con0 ? r/w 8 00h 0f280h serial port 0 transmit/receive buffer l sio0bufl r/w 8/16 00h 0f281h serial port 0 transmit/receive buffer h sio0bufh sio0buf r/w 8 00h
ml610q407/ml610q408/ml610q409 user's manual appendix a registers appendix a-4 address name symbol (byte) symbol (word) r/w size initial value 0f282h serial port 0 control register sio0con ? r/w 8 00h 0f284h serial port 0 mode r egister 0 sio0mod0 r/w 8/16 00h 0f285h serial port 0 mode register 1 sio0mod1 sio0mod r/w 8 00h 0f288h serial port 1 transmit/recei ve buffer l sio1bufl sio1buf r/w 8/16 00h 0f289h serial port 1 transmit/receive buffer h sio1bufh r/w 8 00h 0f28ah serial port 1 control register sio1con ? r/w 8 00h 0f28ch serial port 1 mode register 0 sio1mod0 sio1mod r/w 8/16 00h 0f28dh serial port 1 mode register 1 sio1mod1 r/w 8 00h 0f290h uart0 transmit/receive buffer ua0buf ? r/w 8 00h 0f291h uart0 control register ua0con ? r/w 8 00h 0f292h uart0 mode register 0 ua0mod0 r/w 8/16 00h 0f293h uart0 mode register 1 ua0mod1 ua0mod r/w 8 00h 0f294h uart0 baud rate l is: ua0brtl r/w 8/16 0ffh 0f295h uart0 baud rate register h ua0brth ua0brt r/w 8 0fh 0f296h uart0 status register ua0stat ? r/w 8 00h 0f2c0h melody 0 control register md0con ? r/w 8 00h 0f2c1h melody 0 tempo code register md0tmp ? r/w 8 00h 0f2c2h melody 0 scale code register md0ton r/w 8/16 00h 0f2c3h melody 0 tone length code register md0len md0tl r/w 8 00h 0f300h rc-adc counter a regi ster 0 radca0 ? r/w 8 00h 0f301h rc-adc counter a regi ster 1 radca1 ? r/w 8 00h 0f304h rc-adc counter b regi ster 0 radcb0 ? r/w 8 00h 0f305h rc-adc counter b regi ster 1 radcb1 ? r/w 8 00h 0f308h rc-adc mode register radmod ? r/w 8 00h 0f309h rc-adc control register radcon ? r/w 8 00h 0f400h display allocation register a ds0c0a ? r/w 8 undefined 0f401h display allocation register a ds1c0a ? r/w 8 undefined 0f402h display allocation register a ds2c0a ? r/w 8 undefined 0f403h display allocation register a ds3c0a ? r/w 8 undefined 0f404h display allocation register a ds4c0a ? r/w 8 undefined 0f405h display allocation register a ds5c0a ? r/w 8 undefined 0f406h display allocation register a ds6c0a ? r/w 8 undefined 0f407h display allocation register a ds7c0a ? r/w 8 undefined 0f408h display allocation register a ds8c0a ? r/w 8 undefined 0f409h display allocation register a ds9c0a ? r/w 8 undefined 0f40ah display allocation register a ds10c0a ? r/w 8 undefined 0f40bh display allocation register a ds11c0a ? r/w 8 undefined 0f40ch display allocation register a ds12c0a ? r/w 8 undefined 0f40dh display allocation register a ds13c0a ? r/w 8 undefined 0f40eh display allocation register a ds14c0a ? r/w 8 undefined 0f40fh display allocation register a ds15c0a ? r/w 8 undefined 0f410h display allocation register a ds16c0a ? r/w 8 undefined 0f411h display allocation register a ds17c0a ? r/w 8 undefined 0f412h display allocation register a ds18c0a ? r/w 8 undefined 0f413h display allocation register a ds19c0a ? r/w 8 undefined 0f414h display allocation register a ds20c0a ? r/w 8 undefined 0f415h display allocation register a ds21c0a ? r/w 8 undefined 0f416h display allocation register a ds22c0a ? r/w 8 undefined
ml610q407/ml610q408/ml610q409 user's manual appendix a registers appendix a-5 address name symbol (byte) symbol (word) r/w size initial value 0f417h display allocation register a ds23c0a ? r/w 8 undefined 0f418h display allocation register a ds24c0a ? r/w 8 undefined 0f419h display allocation register a ds25c0a ? r/w 8 undefined 0f41ah display allocation register a ds26c0a ? r/w 8 undefined 0f41bh display allocation register a ds27c0a ? r/w 8 undefined 0f41ch display allocation register a ds28c0a ? r/w 8 undefined 0f41dh display allocation register a ds29c0a ? r/w 8 undefined 0f41eh display allocation register a ds30c0a ? r/w 8 undefined 0f41fh display allocation register a ds31c0a ? r/w 8 undefined 0f420h display allocation register a ds32c0a ? r/w 8 undefined 0f421h display allocation register a ds33c0a ? r/w 8 undefined 0f422h display allocation register a ds34c0a ? r/w 8 undefined 0f423h display allocation register a ds35c0a ? r/w 8 undefined 0f424h display allocation register a ds36c0a ? r/w 8 undefined 0f425h display allocation register a ds37c0a ? r/w 8 undefined 0f426h display allocation register a ds38c0a ? r/w 8 undefined 0f427h display allocation register a ds39c0a ? r/w 8 undefined 0f440h display allocation register a ds0c1a ? r/w 8 undefined 0f441h display allocation register a ds1c1a ? r/w 8 undefined 0f442h display allocation register a ds2c1a ? r/w 8 undefined 0f443h display allocation register a ds3c1a ? r/w 8 undefined 0f444h display allocation register a ds4c1a ? r/w 8 undefined 0f445h display allocation register a ds5c1a ? r/w 8 undefined 0f446h display allocation register a ds6c1a ? r/w 8 undefined 0f447h display allocation register a ds7c1a ? r/w 8 undefined 0f448h display allocation register a ds8c1a ? r/w 8 undefined 0f449h display allocation register a ds9c1a ? r/w 8 undefined 0f44ah display allocation register a ds10c1a ? r/w 8 undefined 0f44bh display allocation register a ds11c1a ? r/w 8 undefined 0f44ch display allocation register a ds12c1a ? r/w 8 undefined 0f44dh display allocation register a ds13c1a ? r/w 8 undefined 0f44eh display allocation register a ds14c1a ? r/w 8 undefined 0f44fh display allocation register a ds15c1a ? r/w 8 undefined 0f450h display allocation register a ds16c1a ? r/w 8 undefined 0f451h display allocation register a ds17c1a ? r/w 8 undefined 0f452h display allocation register a ds18c1a ? r/w 8 undefined 0f453h display allocation register a ds19c1a ? r/w 8 undefined 0f454h display allocation register a ds20c1a ? r/w 8 undefined 0f455h display allocation register a ds21c1a ? r/w 8 undefined 0f456h display allocation register a ds22c1a ? r/w 8 undefined 0f457h display allocation register a ds23c1a ? r/w 8 undefined 0f458h display allocation register a ds24c1a ? r/w 8 undefined 0f459h display allocation register a ds25c1a ? r/w 8 undefined 0f45ah display allocation register a ds26c1a ? r/w 8 undefined 0f45bh display allocation register a ds27c1a ? r/w 8 undefined 0f45ch display allocation register a ds28c1a ? r/w 8 undefined 0f45dh display allocation register a ds29c1a ? r/w 8 undefined
ml610q407/ml610q408/ml610q409 user's manual appendix a registers appendix a-6 address name symbol (byte) symbol (word) r/w size initial value 0f45eh display allocation register a ds30c1a ? r/w 8 undefined 0f45fh display allocation register a ds31c1a ? r/w 8 undefined 0f460h display allocation register a ds32c1a ? r/w 8 undefined 0f461h display allocation register a ds33c1a ? r/w 8 undefined 0f462h display allocation register a ds34c1a ? r/w 8 undefined 0f463h display allocation register a ds35c1a ? r/w 8 undefined 0f464h display allocation register a ds36c1a ? r/w 8 undefined 0f465h display allocation register a ds37c1a ? r/w 8 undefined 0f466h display allocation register a ds38c1a ? r/w 8 undefined 0f467h display allocation register a ds39c1a ? r/w 8 undefined 0f480h display allocation register a ds0c2a ? r/w 8 undefined 0f481h display allocation register a ds1c2a ? r/w 8 undefined 0f482h display allocation register a ds2c2a ? r/w 8 undefined 0f483h display allocation register a ds3c2a ? r/w 8 undefined 0f484h display allocation register a ds4c2a ? r/w 8 undefined 0f485h display allocation register a ds5c2a ? r/w 8 undefined 0f486h display allocation register a ds6c2a ? r/w 8 undefined 0f487h display allocation register a ds7c2a ? r/w 8 undefined 0f488h display allocation register a ds8c2a ? r/w 8 undefined 0f489h display allocation register a ds9c2a ? r/w 8 undefined 0f48ah display allocation register a ds10c2a ? r/w 8 undefined 0f48bh display allocation register a ds11c2a ? r/w 8 undefined 0f48ch display allocation register a ds12c2a ? r/w 8 undefined 0f48dh display allocation register a ds13c2a ? r/w 8 undefined 0f48eh display allocation register a ds14c2a ? r/w 8 undefined 0f48fh display allocation register a ds15c2a ? r/w 8 undefined 0f490h display allocation register a ds16c2a ? r/w 8 undefined 0f491h display allocation register a ds17c2a ? r/w 8 undefined 0f492h display allocation register a ds18c2a ? r/w 8 undefined 0f493h display allocation register a ds19c2a ? r/w 8 undefined 0f494h display allocation register a ds20c2a ? r/w 8 undefined 0f495h display allocation register a ds21c2a ? r/w 8 undefined 0f496h display allocation register a ds22c2a ? r/w 8 undefined 0f497h display allocation register a ds23c2a ? r/w 8 undefined 0f498h display allocation register a ds24c2a ? r/w 8 undefined 0f499h display allocation register a ds25c2a ? r/w 8 undefined 0f49ah display allocation register a ds26c2a ? r/w 8 undefined 0f49bh display allocation register a ds27c2a ? r/w 8 undefined 0f49ch display allocation register a ds28c2a ? r/w 8 undefined 0f49dh display allocation register a ds29c2a ? r/w 8 undefined 0f49eh display allocation register a ds30c2a ? r/w 8 undefined 0f49fh display allocation register a ds31c2a ? r/w 8 undefined 0f4a0h display allocation register a ds32c2a ? r/w 8 undefined 0f4a1h display allocation register a ds33c2a ? r/w 8 undefined 0f4a2h display allocation register a ds34c2a ? r/w 8 undefined 0f4a3h display allocation register a ds35c2a ? r/w 8 undefined 0f4a4h display allocation register a ds36c2a ? r/w 8 undefined 0f4a5h display allocation register a ds37c2a ? r/w 8 undefined
ml610q407/ml610q408/ml610q409 user's manual appendix a registers appendix a-7 address name symbol (byte) symbol (word) r/w size initial value 0f4a6h display allocation register a ds38c2a ? r/w 8 undefined 0f4a7h display allocation register a ds39c2a ? r/w 8 undefined 0f4c0h display allocation register a ds0c3a ? r/w 8 undefined 0f4c1h display allocation register a ds1c3a ? r/w 8 undefined 0f4c2h display allocation register a ds2c3a ? r/w 8 undefined 0f4c3h display allocation register a ds3c3a ? r/w 8 undefined 0f4c4h display allocation register a ds4c3a ? r/w 8 undefined 0f4c5h display allocation register a ds5c3a ? r/w 8 undefined 0f4c6h display allocation register a ds6c3a ? r/w 8 undefined 0f4c7h display allocation register a ds7c3a ? r/w 8 undefined 0f4c8h display allocation register a ds8c3a ? r/w 8 undefined 0f4c9h display allocation register a ds9c3a ? r/w 8 undefined 0f4cah display allocation register a ds10c3a ? r/w 8 undefined 0f4cbh display allocation register a ds11c3a ? r/w 8 undefined 0f4cch display allocation register a ds12c3a ? r/w 8 undefined 0f4cdh display allocation register a ds13c3a ? r/w 8 undefined 0f4ceh display allocation register a ds14c3a ? r/w 8 undefined 0f4cfh display allocation register a ds15c3a ? r/w 8 undefined 0f4d0h display allocation register a ds16c3a ? r/w 8 undefined 0f4d1h display allocation register a ds17c3a ? r/w 8 undefined 0f4d2h display allocation register a ds18c3a ? r/w 8 undefined 0f4d3h display allocation register a ds19c3a ? r/w 8 undefined 0f4d4h display allocation register a ds20c3a ? r/w 8 undefined 0f4d5h display allocation register a ds21c3a ? r/w 8 undefined 0f4d6h display allocation register a ds22c3a ? r/w 8 undefined 0f4d7h display allocation register a ds23c3a ? r/w 8 undefined 0f4d8h display allocation register a ds24c3a ? r/w 8 undefined 0f4d9h display allocation register a ds25c3a ? r/w 8 undefined 0f4dah display allocation register a ds26c3a ? r/w 8 undefined 0f4dbh display allocation register a ds27c3a ? r/w 8 undefined 0f4dch display allocation register a ds28c3a ? r/w 8 undefined 0f4ddh display allocation register a ds29c3a ? r/w 8 undefined 0f4deh display allocation register a ds30c3a ? r/w 8 undefined 0f4dfh display allocation register a ds31c3a ? r/w 8 undefined 0f4e0h display allocation register a ds32c3a ? r/w 8 undefined 0f4e1h display allocation register a ds33c3a ? r/w 8 undefined 0f4e2h display allocation register a ds34c3a ? r/w 8 undefined 0f4e3h display allocation register a ds35c3a ? r/w 8 undefined 0f4e4h display allocation register a ds36c3a ? r/w 8 undefined 0f4e5h display allocation register a ds37c3a ? r/w 8 undefined 0f4e6h display allocation register a ds38c3a ? r/w 8 undefined 0f4e7h display allocation register a ds39c3a ? r/w 8 undefined 0f500h display allocation register a ds0c4a ? r/w 8 undefined 0f501h display allocation register a ds1c4a ? r/w 8 undefined 0f502h display allocation register a ds2c4a ? r/w 8 undefined 0f503h display allocation register a ds3c4a ? r/w 8 undefined 0f504h display allocation register a ds4c4a ? r/w 8 undefined 0f505h display allocation register a ds5c4a ? r/w 8 undefined
ml610q407/ml610q408/ml610q409 user's manual appendix a registers appendix a-8 address name symbol (byte) symbol (word) r/w size initial value 0f506h display allocation register a ds6c4a ? r/w 8 undefined 0f507h display allocation register a ds7c4a ? r/w 8 undefined 0f508h display allocation register a ds8c4a ? r/w 8 undefined 0f509h display allocation register a ds9c4a ? r/w 8 undefined 0f50ah display allocation register a ds10c4a ? r/w 8 undefined 0f50bh display allocation register a ds11c4a ? r/w 8 undefined 0f50ch display allocation register a ds12c4a ? r/w 8 undefined 0f50dh display allocation register a ds13c4a ? r/w 8 undefined 0f50eh display allocation register a ds14c4a ? r/w 8 undefined 0f50fh display allocation register a ds15c4a ? r/w 8 undefined 0f510h display allocation register a ds16c4a ? r/w 8 undefined 0f511h display allocation register a ds17c4a ? r/w 8 undefined 0f512h display allocation register a ds18c4a ? r/w 8 undefined 0f513h display allocation register a ds19c4a ? r/w 8 undefined 0f514h display allocation register a ds20c4a ? r/w 8 undefined 0f515h display allocation register a ds21c4a ? r/w 8 undefined 0f516h display allocation register a ds22c4a ? r/w 8 undefined 0f517h display allocation register a ds23c4a ? r/w 8 undefined 0f518h display allocation register a ds24c4a ? r/w 8 undefined 0f519h display allocation register a ds25c4a ? r/w 8 undefined 0f51ah display allocation register a ds26c4a ? r/w 8 undefined 0f51bh display allocation register a ds27c4a ? r/w 8 undefined 0f51ch display allocation register a ds28c4a ? r/w 8 undefined 0f51dh display allocation register a ds29c4a ? r/w 8 undefined 0f51eh display allocation register a ds30c4a ? r/w 8 undefined 0f51fh display allocation register a ds31c4a ? r/w 8 undefined 0f520h display allocation register a ds32c4a ? r/w 8 undefined 0f521h display allocation register a ds33c4a ? r/w 8 undefined 0f522h display allocation register a ds34c4a ? r/w 8 undefined 0f523h display allocation register a ds35c4a ? r/w 8 undefined 0f524h display allocation register a ds36c4a ? r/w 8 undefined 0f525h display allocation register a ds37c4a ? r/w 8 undefined 0f526h display allocation register a ds38c4a ? r/w 8 undefined 0f527h display allocation register a ds39c4a ? r/w 8 undefined 0f600h display allocation register b ds0c0b ? r/w 8 undefined 0f601h display allocation register b ds1c0b ? r/w 8 undefined 0f602h display allocation register b ds2c0b ? r/w 8 undefined 0f603h display allocation register b ds3c0b ? r/w 8 undefined 0f604h display allocation register b ds4c0b ? r/w 8 undefined 0f605h display allocation register b ds5c0b ? r/w 8 undefined 0f606h display allocation register b ds6c0b ? r/w 8 undefined 0f607h display allocation register b ds7c0b ? r/w 8 undefined 0f608h display allocation register b ds8c0b ? r/w 8 undefined 0f609h display allocation register b ds9c0b ? r/w 8 undefined 0f60ah display allocation register b ds10c0b ? r/w 8 undefined 0f60bh display allocation register b ds11c0b ? r/w 8 undefined 0f60ch display allocation register b ds12c0b ? r/w 8 undefined 0f60dh display allocation register b ds13c0b ? r/w 8 undefined
ml610q407/ml610q408/ml610q409 user's manual appendix a registers appendix a-9 address name symbol (byte) symbol (word) r/w size initial value 0f60eh display allocation register b ds14c0b ? r/w 8 undefined 0f60fh display allocation register b ds15c0b ? r/w 8 undefined 0f610h display allocation register b ds16c0b ? r/w 8 undefined 0f611h display allocation register b ds17c0b ? r/w 8 undefined 0f612h display allocation register b ds18c0b ? r/w 8 undefined 0f613h display allocation register b ds19c0b ? r/w 8 undefined 0f614h display allocation register b ds20c0b ? r/w 8 undefined 0f615h display allocation register b ds21c0b ? r/w 8 undefined 0f616h display allocation register b ds22c0b ? r/w 8 undefined 0f617h display allocation register b ds23c0b ? r/w 8 undefined 0f618h display allocation register b ds24c0b ? r/w 8 undefined 0f619h display allocation register b ds25c0b ? r/w 8 undefined 0f61ah display allocation register b ds26c0b ? r/w 8 undefined 0f61bh display allocation register b ds27c0b ? r/w 8 undefined 0f61ch display allocation register b ds28c0b ? r/w 8 undefined 0f61dh display allocation register b ds29c0b ? r/w 8 undefined 0f61eh display allocation register b ds30c0b ? r/w 8 undefined 0f61fh display allocation register b ds31c0b ? r/w 8 undefined 0f620h display allocation register b ds32c0b ? r/w 8 undefined 0f621h display allocation register b ds33c0b ? r/w 8 undefined 0f622h display allocation register b ds34c0b ? r/w 8 undefined 0f623h display allocation register b ds35c0b ? r/w 8 undefined 0f624h display allocation register b ds36c0b ? r/w 8 undefined 0f625h display allocation register b ds37c0b ? r/w 8 undefined 0f626h display allocation register b ds38c0b ? r/w 8 undefined 0f627h display allocation register b ds39c0b ? r/w 8 undefined 0f640h display allocation register b ds0c1b ? r/w 8 undefined 0f641h display allocation register b ds1c1b ? r/w 8 undefined 0f642h display allocation register b ds2c1b ? r/w 8 undefined 0f643h display allocation register b ds3c1b ? r/w 8 undefined 0f644h display allocation register b ds4c1b ? r/w 8 undefined 0f645h display allocation register b ds5c1b ? r/w 8 undefined 0f646h display allocation register b ds6c1b ? r/w 8 undefined 0f647h display allocation register b ds7c1b ? r/w 8 undefined 0f648h display allocation register b ds8c1b ? r/w 8 undefined 0f649h display allocation register b ds9c1b ? r/w 8 undefined 0f64ah display allocation register b ds10c1b ? r/w 8 undefined 0f64bh display allocation register b ds11c1b ? r/w 8 undefined 0f64ch display allocation register b ds12c1b ? r/w 8 undefined 0f64dh display allocation register b ds13c1b ? r/w 8 undefined 0f64eh display allocation register b ds14c1b ? r/w 8 undefined 0f64fh display allocation register b ds15c1b ? r/w 8 undefined 0f650h display allocation register b ds16c1b ? r/w 8 undefined 0f651h display allocation register b ds17c1b ? r/w 8 undefined 0f652h display allocation register b ds18c1b ? r/w 8 undefined 0f653h display allocation register b ds19c1b ? r/w 8 undefined 0f654h display allocation register b ds20c1b ? r/w 8 undefined 0f655h display allocation register b ds21c1b ? r/w 8 undefined
ml610q407/ml610q408/ml610q409 user's manual appendix a registers appendix a-10 address name symbol (byte) symbol (word) r/w size initial value 0f656h display allocation register b ds22c1b ? r/w 8 undefined 0f657h display allocation register b ds23c1b ? r/w 8 undefined 0f658h display allocation register b ds24c1b ? r/w 8 undefined 0f659h display allocation register b ds25c1b ? r/w 8 undefined 0f65ah display allocation register b ds26c1b ? r/w 8 undefined 0f65bh display allocation register b ds27c1b ? r/w 8 undefined 0f65ch display allocation register b ds28c1b ? r/w 8 undefined 0f65dh display allocation register b ds29c1b ? r/w 8 undefined 0f65eh display allocation register b ds30c1b ? r/w 8 undefined 0f65fh display allocation register b ds31c1b ? r/w 8 undefined 0f660h display allocation register b ds32c1b ? r/w 8 undefined 0f661h display allocation register b ds33c1b ? r/w 8 undefined 0f662h display allocation register b ds34c1b ? r/w 8 undefined 0f663h display allocation register b ds35c1b ? r/w 8 undefined 0f664h display allocation register b ds36c1b ? r/w 8 undefined 0f665h display allocation register b ds37c1b ? r/w 8 undefined 0f666h display allocation register b ds38c1b ? r/w 8 undefined 0f667h display allocation register b ds39c1b ? r/w 8 undefined 0f680h display allocation register b ds0c2b ? r/w 8 undefined 0f681h display allocation register b ds1c2b ? r/w 8 undefined 0f682h display allocation register b ds2c2b ? r/w 8 undefined 0f683h display allocation register b ds3c2b ? r/w 8 undefined 0f684h display allocation register b ds4c2b ? r/w 8 undefined 0f685h display allocation register b ds5c2b ? r/w 8 undefined 0f686h display allocation register b ds6c2b ? r/w 8 undefined 0f687h display allocation register b ds7c2b ? r/w 8 undefined 0f688h display allocation register b ds8c2b ? r/w 8 undefined 0f689h display allocation register b ds9c2b ? r/w 8 undefined 0f68ah display allocation register b ds10c2b ? r/w 8 undefined 0f68bh display allocation register b ds11c2b ? r/w 8 undefined 0f68ch display allocation register b ds12c2b ? r/w 8 undefined 0f68dh display allocation register b ds13c2b ? r/w 8 undefined 0f68eh display allocation register b ds14c2b ? r/w 8 undefined 0f68fh display allocation register b ds15c2b ? r/w 8 undefined 0f690h display allocation register b ds16c2b ? r/w 8 undefined 0f691h display allocation register b ds17c2b ? r/w 8 undefined 0f692h display allocation register b ds18c2b ? r/w 8 undefined 0f693h display allocation register b ds19c2b ? r/w 8 undefined 0f694h display allocation register b ds20c2b ? r/w 8 undefined 0f695h display allocation register b ds21c2b ? r/w 8 undefined 0f696h display allocation register b ds22c2b ? r/w 8 undefined 0f697h display allocation register b ds23c2b ? r/w 8 undefined 0f698h display allocation register b ds24c2b ? r/w 8 undefined 0f699h display allocation register b ds25c2b ? r/w 8 undefined 0f69ah display allocation register b ds26c2b ? r/w 8 undefined 0f69bh display allocation register b ds27c2b ? r/w 8 undefined 0f69ch display allocation register b ds28c2b ? r/w 8 undefined 0f69dh display allocation register b ds29c2b ? r/w 8 undefined
ml610q407/ml610q408/ml610q409 user's manual appendix a registers appendix a-11 address name symbol (byte) symbol (word) r/w size initial value 0f69eh display allocation register b ds30c2b ? r/w 8 undefined 0f69fh display allocation register b ds31c2b ? r/w 8 undefined 0f6a0h display allocation register b ds32c2b ? r/w 8 undefined 0f6a1h display allocation register b ds33c2b ? r/w 8 undefined 0f6a2h display allocation register b ds34c2b ? r/w 8 undefined 0f6a3h display allocation register b ds35c2b ? r/w 8 undefined 0f6a4h display allocation register b ds36c2b ? r/w 8 undefined 0f6a5h display allocation register b ds37c2b ? r/w 8 undefined 0f6a6h display allocation register b ds38c2b ? r/w 8 undefined 0f6a7h display allocation register b ds39c2b ? r/w 8 undefined 0f6c0h display allocation register b ds0c3b ? r/w 8 undefined 0f6c1h display allocation register b ds1c3b ? r/w 8 undefined 0f6c2h display allocation register b ds2c3b ? r/w 8 undefined 0f6c3h display allocation register b ds3c3b ? r/w 8 undefined 0f6c4h display allocation register b ds4c3b ? r/w 8 undefined 0f6c5h display allocation register b ds5c3b ? r/w 8 undefined 0f6c6h display allocation register b ds6c3b ? r/w 8 undefined 0f6c7h display allocation register b ds7c3b ? r/w 8 undefined 0f6c8h display allocation register b ds8c3b ? r/w 8 undefined 0f6c9h display allocation register b ds9c3b ? r/w 8 undefined 0f6cah display allocation register b ds10c3b ? r/w 8 undefined 0f6cbh display allocation register b ds11c3b ? r/w 8 undefined 0f6cch display allocation register b ds12c3b ? r/w 8 undefined 0f6cdh display allocation register b ds13c3b ? r/w 8 undefined 0f6ceh display allocation register b ds14c3b ? r/w 8 undefined 0f6cfh display allocation register b ds15c3b ? r/w 8 undefined 0f6d0h display allocation register b ds16c3b ? r/w 8 undefined 0f6d1h display allocation register b ds17c3b ? r/w 8 undefined 0f6d2h display allocation register b ds18c3b ? r/w 8 undefined 0f6d3h display allocation register b ds19c3b ? r/w 8 undefined 0f6d4h display allocation register b ds20c3b ? r/w 8 undefined 0f6d5h display allocation register b ds21c3b ? r/w 8 undefined 0f6d6h display allocation register b ds22c3b ? r/w 8 undefined 0f6d7h display allocation register b ds23c3b ? r/w 8 undefined 0f6d8h display allocation register b ds24c3b ? r/w 8 undefined 0f6d9h display allocation register b ds25c3b ? r/w 8 undefined 0f6dah display allocation register b ds26c3b ? r/w 8 undefined 0f6dbh display allocation register b ds27c3b ? r/w 8 undefined 0f6dch display allocation register b ds28c3b ? r/w 8 undefined 0f6ddh display allocation register b ds29c3b ? r/w 8 undefined 0f6deh display allocation register b ds30c3b ? r/w 8 undefined 0f6dfh display allocation register b ds31c3b ? r/w 8 undefined 0f6e0h display allocation register b ds32c3b ? r/w 8 undefined 0f6e1h display allocation register b ds33c3b ? r/w 8 undefined 0f6e2h display allocation register b ds34c3b ? r/w 8 undefined 0f6e3h display allocation register b ds35c3b ? r/w 8 undefined 0f6e4h display allocation register b ds36c3b ? r/w 8 undefined 0f6e5h display allocation register b ds37c3b ? r/w 8 undefined
ml610q407/ml610q408/ml610q409 user's manual appendix a registers appendix a-12 address name symbol (byte) symbol (word) r/w size initial value 0f6e6h display allocation register b ds38c3b ? r/w 8 undefined 0f6e7h display allocation register b ds39c3b ? r/w 8 undefined 0f700h display allocation register b ds0c4b ? r/w 8 undefined 0f701h display allocation register b ds1c4b ? r/w 8 undefined 0f702h display allocation register b ds2c4b ? r/w 8 undefined 0f703h display allocation register b ds3c4b ? r/w 8 undefined 0f704h display allocation register b ds4c4b ? r/w 8 undefined 0f705h display allocation register b ds5c4b ? r/w 8 undefined 0f706h display allocation register b ds6c4b ? r/w 8 undefined 0f707h display allocation register b ds7c4b ? r/w 8 undefined 0f708h display allocation register b ds8c4b ? r/w 8 undefined 0f709h display allocation register b ds9c4b ? r/w 8 undefined 0f70ah display allocation register b ds10c4b ? r/w 8 undefined 0f70bh display allocation register b ds11c4b ? r/w 8 undefined 0f70ch display allocation register b ds12c4b ? r/w 8 undefined 0f70dh display allocation register b ds13c4b ? r/w 8 undefined 0f70eh display allocation register b ds14c4b ? r/w 8 undefined 0f70fh display allocation register b ds15c4b ? r/w 8 undefined 0f710h display allocation register b ds16c4b ? r/w 8 undefined 0f711h display allocation register b ds17c4b ? r/w 8 undefined 0f712h display allocation register b ds18c4b ? r/w 8 undefined 0f713h display allocation register b ds19c4b ? r/w 8 undefined 0f714h display allocation register b ds20c4b ? r/w 8 undefined 0f715h display allocation register b ds21c4b ? r/w 8 undefined 0f716h display allocation register b ds22c4b ? r/w 8 undefined 0f717h display allocation register b ds23c4b ? r/w 8 undefined 0f718h display allocation register b ds24c4b ? r/w 8 undefined 0f719h display allocation register b ds25c4b ? r/w 8 undefined 0f71ah display allocation register b ds26c4b ? r/w 8 undefined 0f71bh display allocation register b ds27c4b ? r/w 8 undefined 0f71ch display allocation register b ds28c4b ? r/w 8 undefined 0f71dh display allocation register b ds29c4b ? r/w 8 undefined 0f71eh display allocation register b ds30c4b ? r/w 8 undefined 0f71fh display allocation register b ds31c4b ? r/w 8 undefined 0f720h display allocation register b ds32c4b ? r/w 8 undefined 0f721h display allocation register b ds33c4b ? r/w 8 undefined 0f722h display allocation register b ds34c4b ? r/w 8 undefined 0f723h display allocation register b ds35c4b ? r/w 8 undefined 0f724h display allocation register b ds36c4b ? r/w 8 undefined 0f725h display allocation register b ds37c4b ? r/w 8 undefined 0f726h display allocation register b ds38c4b ? r/w 8 undefined 0f727h display allocation register b ds39c4b ? r/w 8 undefined (*1) ml610q407 and ml610q408 have this register, but ml610q409 does not have it. (*2) initial value for ml610q407 (*3) initial value for ml610q408
ml610q407/ml610q408/ml610q409 user's manual appendix b package dimensions b-1 appendix b package dimensions (unit: mm) p-tqfp100-1414-0.50-zk package material epoxy resin lead frame material cu alloy lead finish sn-2bi (bi 2%typ.) solder thickness more than 5 m package weight (g) 0.55typ. rev. no./last revised 2 / oct. 22,2009 notes for mounting the surface mount type package the surface mount type packages are very susceptible to heat in reflow moun ting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact our responsible sales person on the product name, package name, pin number, package code and desired mounting c onditions (reflow method, temperature and times).
ml610q407/ml610q408/ml610q409 user's manual appendix c electrical characteristics appendix c-1 appendix c electrical characteristics z absolute maximum ratings (v ss = 0v) parameter symbol condition rating unit power supply voltage 1 v dd ta=25c -0.3 to +4.6 v power supply voltage 2 v pp ta=25c -0.3 to +9.5 v power supply voltage 3 v ddl ta=25c -0.3 to +3.6 v power supply voltage 4 v l1 ta=25c -0.3 to +2.0 v power supply voltage 5 v l2 ta=25c -0.3 to +4.0 v power supply voltage 6 v l3 ta=25c -0.3 to +6.0 v input voltage v in ta=25c -0.3 to v dd +0.3 v output voltage v out ta=25c -0.3 to v dd +0.3 v output current 1 i out1 port 3 to 6, ta=25c -12 to +11 ma output current 2 i out2 port 2, ta=25c -12 to +20 ma power dissipation pd ta=25c 0.9 w storage temperature t stg D -55 to +150 ? z recommended operation condition (v ss = 0v) parameter symbol condition range unit without p version -20 to +70 operating temperature t op p version -40 to +85 ? f op =30k to 625khz 1.25 to 3.6 operating voltage v dd f op =30k to 2.5mhz 1.8 to 3.6 v v dd =1.25 to 3.6v 30k to 625k operating frequency (cpu) f op v dd =1.8 to 3.6v 30k to 2.5m hz low-speed crystal oscillation frequency f xtl D 32.768k hz c dl D 3 to 18 low-speed crystal oscillation external capacitance c gl D 3 to 18 pf v ddl pin external capacitance c l D 0.4730% f v l1, 2, or 3 pin external capacitance c a,b,c D 0.130% f pin-to-pin (c1 to c2) external capacitance c 12 D 0.4730% f
ml610q407/ml610q408/ml610q409 user's manual appendix c electrical characteristics appendix c?2 z operating conditions of flash memory (v ss = 0v) parameter symbol condition range unit operating temperature t op at write/erase 0 to +40 c v dd at write/erase 2.75 to 3.6 v ddl at write/erase *1 2.5 to 2.75 operating voltage v pp at write/erase 7.7 to 8.3 v rewrite count c ep D 80 cycles data retention y dr D 10 years *1 : when writing to and erasing on the flash memory, the vo ltage in the specified range needs to be supplied to the v ddl pin. the v pp pin has an internal pull-down resistor. z dc characteristics (1/5) (v dd = 1.25 to 3.6v, v ss =0v, ta= -20 to +70c, ta= -40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit measur ement circuit ta=25 c typ. -10% 500 typ. +10% khz v dd =1.25 to 3.6v * 3 typ. -25% 500 typ. +25% khz ta=25 c typ. -10% 2.0 typ. +10% khz 500khz/2mhz rc oscillation frequency f rc v dd =1.8 to 3.6v * 3 typ. -25% 2.0 typ. +25 % mhz low-speed crystal oscillation start time* 2 t xtl D D 0.6 2 s 500khz/2mhz rc oscillation start time t rc D D D 3 s low-speed oscillation stop detect time *1 t stop D 12 16.4 41 ms reset pulse width p rst D 200 D D reset noise elimination pulse width p nrst D D D 0.3 s power-on reset generated power rise time t por D D D 10 ms 1 * 1 : when low-speed crystal oscillation stops for a duration more th an the low-speed oscillation stop detect time, the system is r eset to shift to system reset mode. * 2 : 32.768khz crystal resonator dt-26 (load capacitanc e 6pf) (made by kds:daishinku corp.) is used (c gl =c dl =12pf). * 3 : recommended operating temperature (ta=-20 to 70 c, ta=-40 to 85 c for p version) z reset reset_n reset_n pin reset v dd 0.9 v dd 0.1 v dd t por power on reset p rst vil1 vil1
ml610q407/ml610q408/ml610q409 user's manual appendix c electrical characteristics appendix c-3 z dc characteristics (2/5) (v dd = 1.25 to 3.6v, v ss =0v, ta= -20 to +70c, ta= -40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit measur ement circuit fop=30k to 625khz 1.1 1.2 1.3 v ddl voltage v ddl fop=30k to 2.5mhz 1.35 1.5 1.65 v v ddl temperature deviation * 1 ? v ddl v dd =3.0v D -1 D mv/c v ddl voltage dependency * 1 ? v ddl D D 5 20 mv/v 1 * 1 : the maximum v ddl voltage becomes the v dd voltage level when the v ddl voltage determined by the temperature and voltage deviations mathematically exceeds the v dd voltage.
ml610q407/ml610q408/ml610q409 user's manual appendix c electrical characteristics appendix c?4 z dc characteristics (3/5) (v dd = 3.0v, v ss =0v, ta= -20 to +70c, ta= -40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit measur ement circuit ta=25 c D 0.4 0.8 supply current 1 idd1 cpu: in stop state. low-speed/high-speed oscillation: stopped. * 5 D D 8 a ta=25 c D 0.9 1.8 supply current 2 idd2 cpu: in halt state. (ltbc, wdt: operating)* 3 * 4 . high-speed 500khz/2mhz oscillation: stopped. lcd/bias circuits: operating * 6 * 5 D D 9 a ta=25 c D 5 8 supply current 3 idd3 cpu: in 32.768khz operating state.* 1 * 3 high-speed 500khz/2mhz oscillation: stopped, lcd/bias circuits: operating * 2 * 5 D D 15 a ta=25 c D 70 100 supply current 4-1 idd4-1 cpu: in 500khz rc operating state. lcd/bias circuits: operating.* 2 * 5 D D 120 a ta=25 c D 280 350 supply current 4-2 idd4-2 cpu: in 2mhz rc operating state. lcd/bias circuits: operating.* 2 * 5 D D 400 ma 1 * 1 : when the cpu operating rate is 100% (no halt state). * 2 : all segs: off waveform, no lcd panel load, 1/3 bias, 1/3 duty, frame frequency: approx. 64 hz, bias voltage multiplying clock : 1/128 lsclk (256hz) * 3 : 32.768khz crystal resonator dt-26 (load capacitanc e 6pf) (made by kds:daishinku corp.) is used (c gl =c dl =6pf) * 4 : significant bits of blkcon0 to blkcon4 registers are all ? 1 ? except dlcd bit on blkcon4 . * 5 : recommended operating temperature (ta=-20 to 70 c, ta=-40 to 85 c for p version) * 6 : lcd stop mode, 1/3 bias, bias voltage multiplying clock: 1/128 lsclk (256hz)
ml610q407/ml610q408/ml610q409 user's manual appendix c electrical characteristics appendix c-5 z dc characteristics (4/5) (v dd = 1.25 to 3.6v, v ss =0v, ta= -20 to +70c, ta= -40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit measur ement circuit ioh1=-0.5ma, v dd =1.8 to 3.6v v dd -0.5 D D voh1 ioh1=-0.03ma, v dd =1.25 to 3.6v v dd -0.3 D D iol1=+0.5ma, v dd =1.8 to 3.6v D D 0.5 output voltage 1 (p20 to p22, p24 (n-channel open drain output mode is not selected)) (p30 to p35) (p40 to p47) (p50 to p57) (p60 to p63) *1 *2 (p64 to p67) *1 vol1 iol1=+0.1ma, v dd =1.25 to 3.6v D D 0.3 output voltage 2 (p20 to p22, p24 (n-channel open drain output mode is selected)) vol2 iol2=+5ma, v dd =1.8 to 3.6v D D 0.5 voh3 ioh3=-0.05ma, vl1=1.2v v l3 -0.2 D D voml3 ioml3=+0.05ma, vl1=1.2v D D v l2 +0.2 voml3s ioml3s=-0.05ma, vl1=1.2v v l2 -0.2 D D volm3 iolm3=+0.05ma, vl1=1.2v D D v l1 +0.2 volm3s iolm3s=-0.05ma, vl1=1.2v v l1 -0.2 D D output voltage 3 (com0 to 4) (seg0 to 31) *1 (seg0 to 35) *2 (seg0 to 39) *3 vol3 iol3=+0.05ma, vl1=1.2v D D 0.2 v 2 iooh voh=v dd (in high-impedance state) D D 1 output leakage (p20 to p22,p24) (p30 to p35) (p40 to p47) (p50 to p57) (p60 to p63) *1 *2 (p60 to p67) *1 iool vol=v ss (in high-impedance state) -1 D D a 3 iih1 vih1=v dd D D 1 input current 1 (reset_n) (test1_n) iil1 vil1=v ss -600 -300 -2 iih2 vih2=v dd 2 300 600 input current 2 (test0) iil2 vil2=v ss -1 D D vih3=v dd, v dd =1.8 to 3.6v (when pulled-down) 2 30 200 iih3 vih3=v dd, v dd =1.25 to 3.6v (when pulled-down) 0.01 30 200 vil3=v ss, v dd =1.8 to 3.6v (when pulled-up) -200 -30 -2 iil3 vil3=v ss, v dd =1.25 to 3.6v (when pulled-up) -200 -30 -0.01 iih3z vih3=v dd (in high-impedance state) D D 1 input current 3 (p00 to p04) (p30 to p35) (p40 to p47) (p50 to p57) iil3z vil3=v ss (in high-impedance state) -1 D D a 4 * 1 : characteristics for ml610q407. * 2 : characteristics for ml610q408. * 3 : characteristics for ml610q409.
ml610q407/ml610q408/ml610q409 user's manual appendix c electrical characteristics appendix c?6 z dc characteristics (5/5) (v dd = 1.25 to 3.6v, v ss =0v, ta= -20 to +70c, ta= -40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit measur ement circuit vih1 D 0.7 v dd D v dd v dd =1.8 to 3.6v 0 D 0.3 v dd input voltage 1 (reset_n) (test0, test1_n) (p00 to p04) (p30 to p35) (p40 to p47) (p50 to p57) vil1 v dd =1.25 to 3.6v 0 D 0.2 v dd v 5 input pin capacitance (p00 to p04) (p30 to p35) (p40 to p47) (p50 to p57) cin f=10khz v rms =50mv ta=25 c D D 5 pf D
ml610q407/ml610q408/ml610q409 user's manual appendix c electrical characteristics appendix c-7 z measuring circuit measuring circuit 1 measuring circuit 2 xt0 xt1 a v dd v ddl c l v l1 c a v l2 v l3 c c v ss c2 c1 c 12 c v : 1 f c l : 0.47uf c a ,c b ,c c : 0.1 f c 12 : 0.47 f 32.768khz crystal resonator : dt-26 (load capacitance 6pf) (made by kds:daishinku corp.) c gl , c dl : 6pf c v c dl 32.768khz crystal resonator input pin v v dd v ddl v l1 v l2 v l3 v ss vih vil output pin *1: input logic circuit to determine the specified measuring conditions. (note 2) repeats for t he specified output pin (note 2) (note 1) c gl
ml610q407/ml610q408/ml610q409 user's manual appendix c electrical characteristics appendix c?8 measuring circuit 3 measuring circuit 4 measuring circuit 5 input pin a v dd v ddl v l1 v l2 v l3 v ss vih vil output pin *1: input logic circuit to determine the specified measuring conditions. (note 2) repeats for t he specified output pin (note 2) (note 1) input pin a v dd v ddl v l1 v l2 v l3 v ss output pin (note 3) repeats for t he specified input pin (note 3) input pin v dd v ddl v l1 v l2 v l3 v ss vih vil output pin *1: input logic circuit to determine the specified measurin g conditions. (note 1) waveform observation
ml610q407/ml610q408/ml610q409 user's manual appendix c electrical characteristics appendix c-9 z ac characteristics (external interrupt) (v dd = 1.25 to 3.6v, v ss =0v, ta= -20 to +70c, ta= -40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit external interrupt disable period t nul interrupt: enabled (mie = 1), cpu: nop operation system clock: 32.768khz 76.8 D 106.8 s z ac characteristics (uart) (v dd = 1.25 to 3.6v, v ss =0v, ta= -20 to +70c, ta= -40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit transmit baud rate t tbrt D D brt* 1 D s receive baud rate t rbrt D brt* 1 -3% brt* 1 brt* 1 +3% s * 1 : baud rate period (including the error of the clock frequency sele cted) set with the uart baud rate register (ua0brtl,h) and the uart mode register 0 (ua0mod0). t rbrt txd0* rxd0* *: indicates the secondary function of the port. t tbrt t nul p00 to p04 (rising-edge interrupt mode) p00 to p04 (falling-edge interrupt mode) p00 to p04, p50 to p57 (both-edge interrupt mode) t nul t nul
ml610q407/ml610q408/ml610q409 user's manual appendix c electrical characteristics appendix c?10 z ac characteristics (synchronous serial port) (v dd = 1.25 to 3.6v, v ss =0v, ta= -20 to +70c, ta= -40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit in the 500khz oscillation mode* 2 10 D D s sclk input cycle (slave mode) t scyc in the 2mhz oscillation mode* 3 v dd =1.8 to 3.6v 1 D D s sclk output cycle (master mode) t scyc D D sclk* 1 D s in the 500khz oscillation mode* 2 4 D D s sclk input pulse width (slave mode) t sw in the 2mhz oscillation mode* 3 v dd =1.8 to 3.6v 0.4 D D s sclk output pulse width (master mode) t sw D sclk* 1 0.4 sclk* 1 0.5 sclk* 1 0.6 s in the 500khz oscillation mode* 2 output load 10pf D D 500 sout output delay time (slave mode) t sd in the 2mhz oscillation mode* 3 output load 10pf D D 240 ns in the 500khz oscillation mode* 2 output load 10pf D D 500 sout output delay time (master mode) t sd in the 2mhz oscillation mode* 3 output load 10pf, v dd =1.8 to 3.6v D D 240 ns sin input setup time (slave mode) t ss D 80 D D ns in the 500khz oscillation mode* 2 500 D D sin input setup time (master mode) t ss in the 2mhz oscillation mode* 3 v dd =1.8 to 3.6v 240 D D ns in the 500khz oscillation mode* 2 300 D D sin input hold time t sh in the 2mhz oscillation mode* 3 v dd =1.8 to 3.6v 80 D D ns * 1 : clock cycle selected with s0ck3?0 of the serial port 0 mode register (sio0mod1) * 2 : when 500khz oscillation is selected with rcm of the frequency control register 0 (fcon0) * 3 : when 2mhz oscillation is selected with rcm of the frequency control register 0 (fcon0) t sd sclkn* sinn* soutn* *: indicates the tertiary function of the port (n= 0, 1) t sd t ss t sh t sw t sw t scyc
ml610q407/ml610q408/ml610q409 user's manual appendix c electrical characteristics appendix c-11 z ac characteristics (rc oscillation a/d converter) condition for v dd =1.8 to 3.6v (v dd =1.8 to 3.6v, v ss =0v, ta=-20 to +70c, ta=-40 to +85c fo r p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit oscillation resistor rs0,rs1,rt0, rt0-1,rt1 cs0, ct0, cs1 740pf 1 D D k f osc1 resistor for oscillation=1k 457.3 525.2 575.1 khz f osc2 resistor for oscillation=10k 53.48 58.18 62.43 khz oscillation frequency v dd = 3.0v f osc3 resistor for oscillation=100k 5.43 5.89 6.32 khz kf1 rt0, rt0-1, rt1=1k 7.972 9.028 9.782 ? kf2 rt0, rt0-1, rt1=10k 0.981 1 1.019 ? rs to rt oscillation frequency ratio *1 v dd = 3.0v kf3 rt0, rt0-1, rt1=100k 0.099 0.101 0.104 ? * 1 : kfx is the ratio of the oscillation frequency by the sensor re sistor to the oscillation frequency by the reference resistor o n the same conditions. f oscx (rt0-cs0 oscillation) f oscx (rt0-1-cs0 oscillation) f oscx (rt1-cs1 oscillation) kfx = f oscx (rs0-cs0 oscillation) , f oscx (rs0-cs0 oscillation) , f oscx (rs1-cs1 oscillation) ( x = 1, 2, 3 ) v dd v ddl c l v ss c v rt0, rt0-1, rt1: 1k
/10k
/100k
rs0, rs1: 10k
cs0, ct0, cs1: 560pf cvr0, cvr1: 820pf rcm frequency measurement (f oscx ) input pin vih vil *1: input logic circuit to determine the specified measuring conditions. cs0 rt0 in1 cs1 rs1 rt1 cs0 rs0 rs0 rct0 rt0-1 ct0 rt0 cs1 rs1 rt1 in0 cvr0 cvr1 /puf

ml610q407/ml610q408/ml610q409 user's manual appendix c electrical characteristics appendix c?12 condition for v dd =1.25 to 3.6v (v dd =1.25 to 3.6v, v ss =0v, ta=-20 to +70c, ta=-40 to +85c fo r p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit oscillation resistor rs0,rs1,rt0, rt0-1,rt1 cs0, ct0, cs1 740pf 1 D D k f osc1 resistor for oscillation=6k 81.93 93.16 101.2 khz f osc2 resistor for oscillation=15k 35.32 38.75 41.48 khz oscillation frequency v dd = 1.5v f osc3 resistor for oscillation=105k 5.22 5.65 6.03 khz kf1 rt0, rt0-1, rt1=1k 2.139 2.381 2.632 ? kf2 rt0, rt0-1, rt1=10k 0.973 1 1.028 ? rs to rt oscillation frequency ratio *1 v dd = 1.5v kf3 rt0, rt0-1, rt1=100k 0.142 0.147 0.152 ? f osc1 resistor for oscillation=6k 85.28 94.58 103.3 khz f osc2 resistor for oscillation=15k 35.72 38.87 41.78 khz oscillation frequency v dd = 3.0v f osc3 resistor for oscillation=105k 5.189 5.622 6.012 khz kf1 rt0, rt0-1, rt1=1k 2.227 2.432 2.626 ? kf2 rt0, rt0-1, rt1=10k 0.982 1 1.018 ? rs to rt oscillation frequency ratio *1 v dd = 3.0v kf3 rt0, rt0-1, rt1=100k 0.141 0.145 0.149 ? * 1 : kfx is the ratio of the oscillation frequency by the sensor re sistor to the oscillation frequency by the reference resistor o n the same conditions. f oscx (rt0-cs0 oscillation) f oscx (rt0-1-cs0 oscillation) f oscx (rt1-cs1 oscillation) kfx = f oscx (rs0-cs0 oscillation) , f oscx (rs0-cs0 oscillation) , f oscx (rs1-cs1 oscillation) ( x = 1, 2, 3 ) note: k please have the shortest layout for the co mmon node (wiring patterns which are connected to the external capacitors, resistors and in0/in1 pin), including cvr0/cvr1. especially, do not have long wiring between in0/in1 and rs0/rs1. the coupling capacitance on the wir es may occur incorrect a/d conversion. also, please do not have signals which may be a source of noise around the node. k when rt0/rt1 (thermistor and etc.) requires long wiring due to the restri cted placement, please have v ss (gnd) trace next to the signal. k please make wiring to components (capacitor, resistor, and so on) necessary for objective measurement. wiring to reserved compo nents may affect to the a/d conversion operation by noise the components itself may have. rt0, rt0-1, rt1: 1k
/10k
/100k
ra0, ra0-1, ra1: 5k
rs0, rs1: 15k
cs0, ct0, cs1: 560pf cvr0, cvr1: 820pf frequency measurement (f oscx ) input pin *1: input logic circuit to determine the spec ifi ed m easu rin g co n d i t i o n s . /puf
v dd v ddl c l v ss c v rcm vih vil cs0 rt0 in1 cs1 rs1 rt1 cs0 rs0 rs0 rct0 rt0-1 ct0 rt0 cs1 rs1 in0 cvr0 cvr1 ra1 ra0-1 rt1 ra0
ml610q407/ml610q408/ml610q409 user's manual appendix d application circuit example d-1 appendix d application circuit example figure d-1 ml610q409 application circuit diagram lcd ml610q409 c2 c1 c12 v l3 v l2 v l1 v dd test1_n test0 v pp v ddl v ss c v c p c l 32.768khz crystal resonator c gl c dl xt0 xt1 c c c a reset_n test v pp v ddl v ss uvdd_o vtref com0 to 4 seg0 to 39 p20 p21 p24 p22 buzze r led uease i/f p00 p01 p02 p03 p04 p30/in0 p31/cs0 p34/rct0 p32/rt0 p33/rs0 p35/rcm p44/in1 p45/cs1 p46/rt1 p47/rs1 cs0 rt0 rs0 rt1 rs1 cs1 cvr0 cvr1 p57 p56 p55 p54 p53 p52 p51 p50 key matrix 3.0v reset_n
ml610q407/ml610q408/ml610q409 user's manual appendix e check list appendix e-1 appendix e check list this check list has notes to prevent commonly-made pr ogramming mistakes and frequen tly overlooked or misunderstood hardware features of the mcu. check each note listed up chapter by chapter while coding the program or evaluating it using the mcu. chapter 1 overview ?about unused pins [ ] please confirm how to handle the unused pins (refer to section 1.3.4 in the user?s manual). chapter 2 cpu and memory space ?program memory size [ ] 15,360 byte (0:0000h to 0:3bffh) ?data ram size [ ] 1024 byte (0:e000h to 0:e3ffh) ?unused area [ ] please fill test area 0:3c00h0:3fffh with brk instruction code ?0ffh? (refer to a startup file ?s61040xsw.asm? for program ming in the source code). [ ] for fail safe in your system, please fill unused program memo ry area (your program code does not use) with brk instruction code ?0ffh?. we will fill the area with the code ?0 ffh? at oki semiconductor?s factory programming. ?ram initialization [ ] the hardware reset does not initialize ram. please initialize ram by the software. chapter 3 reset ?reset activation pulse width [ ] minimum 200us (refer to appendix c-2 in the user's manual) ?power-on reset occurrence power rise time [ ] maximum 10ms (refer to appendix c-2 in the user's manual) ?reset status flag [ ] no flag is provided that indicates the occurrence of reset by the reset_n pin (refer to section 3.2.2. in the user's manual). ?brk instruction reset [ ] in system reset by the brk instruction, no special func tion register (sfr) is initialized either. therefore initialize the sfrs by your software (see section 3.3.1 in the user's manual). chapter 4 mcu control function ?stop mode [ ] when the mie flag is "0", the stop code acceptor (stpacp) cannot be enabled under the condition where both the interrupt e nable and request flags become "1" (refer to sections 4.2.2 and 4.2.3. in the user's manual) . [ ] place two nop instructions next to the instruction that sets the stp bit to "1" (refer to section 4.3.3. in the user's manual). ?halt mode [ ] place two nop instructions next to the instruction that sets the hlt bit to "1" (refer to section 4.3.2. in the user's manual). ?blkcon register [ ] blkcon registers enable or disable corresponsive each periphe ral (refer to section 4.2.4 - 4.2.8. in the user?s manual). [ ] when certain bits of block control registers are set to ?1?, corresponding peripherals are reset (all registers are reset) and operating clocks for the peripherals stop. chapter 5 interrupts ?unused interrupt vector table [ ] please define all unused interrupt vector tables for fail safe. ?non-maskable interrupt [ ] the watchdog timer interrupt (wdtint) is a non- maskable interrupt that does not depend on mie flag (refer to sections 5.2.8. and 5.3 in the user's manual) .
ml610q407/ml610q408/ml610q409 user's manual appendix e check list appendix e-2 chapter 6 clock generation circuit ?initial system clock [ ] at power up or system reset, the 32.768khz crystal oscilla tion clock oscillates to be supplied to cpu as the system cloc k. ?switching high-speed clock operation mo de to low-speed clock operation mode [ ] when switching the high-speed clock to the low-speed cloc k after the recovery from the stop mode, make sure the low-spee d clock is oscillating checking to see the low-speed time base counter's q128h bit becomes "1". ?switching high-speed clock operation mode to another high-speed clock operation mode [ ] when switching the high-speed clock mode, the clock must be first switched back to low cloc k before switching to other hig h-speed clock ( refer to section 6.2.2.) . ?port secondary function setting [ ] specify the secondary function for the port 2 when driving a clock to the pin(refer to section 6.4 in the user?s manual). chapter 7 tbc (time base counter) ?htbclk [ ] when using the htbclk for a timer or the pwm, set an arb itrary dividing ratio in the high-speed side time base counter fre quency divide register (htbdr register) ( see section 7.2.3. in the user's manual) . ?how to read ltbc [ ] read consecutively ltbc(low-speed time base counter) twice un til the last data coincides the previous data to prevent read ing of uncertain data while counting up the clock ( refer to section 7.3.1 in the user's manual). chapter 9 timer ?how to read the timer counter registers [ ] check notes for reading the timer counter registers while counting up ( refer to sections 9.2.4 to 9.2.5 in the user's manual). chapter 10 pwm ?pins used [ ] the p24 or p43 pin is used ?how to read the pwm counter registers [ ] check notes for reading the pwm count er registers while the pwm is operating ( refer to section 10.2.4. in the user's manual). ?port secondary and tertiary function setting [ ] when using the p24, set it as the secondary function. when using the p43, set it as the te rtiary function (see sections 15 .2.4 and 17.2.5 in the user's manual). chapter 11 wdt ?overflow period clear wdt during the selected overflow period: [ ] 125ms, [ ] 500ms, [ ] 2s, [ ] 8s ?wdp [ ] check the wdp content before writing to the wdtcon re gister, then determine writing whether "5ah" or "0a5h" ( refer to section 11.2.2. in the user?s manual) . chapter 12 ssio ?pins used [ ] p40(sin0), p41(sck0) and p42(sout0) are used, or p44(sin0), p45(sck0) and p46(sout0) are used. [ ] use the p50 (sin1), p51 (sck1), and p52 (sout1) pins. ?port secondary and tertiary function setting [ ] specify the secondary function for the port( refer to section 12.4 in the user?s manual). chapter 13 uart ?pins used [ ] p02(rxd0) and p43(txd0) are used, or [ ] p42(rxd0) and p43(txd0) are used. [ ] select the p02 or p42 for rxd0 by specifying u0rsel bit of ua0mod0 register. ?port secondary function setting [ ] specify the secondary function for the port( refer to section 13.4 in the user?s manual). chapters 14 to 19 port ?pin handling [ ] don?t leave hi-impedance input ports in floating state. ?port secondary function [ ] specify properly pncon0/1 and pnmod0/1 registers for each port.
ml610q407/ml610q408/ml610q409 user's manual appendix e check list appendix e-3 chapter 20 melody driver ?enabling the lsclk x 2 [ ] set enmlt bit of fcon1 register to ?1? to enable the low- speed double clock (lsclk x 2) before stating the melody or buzze r outputs. ?port secondary function setting [ ] specify the secondary function for the port( refer to section 20.4 in the user?s manual). chapter 21 rc oscillation type a/d converter ?counter register [ ] reading the counter register a or b during the a/d convers ion, returns the data written be fore starting the a/d conversion . ?oscillation monitor pin [ ] p35/rcm pin is a monitor pin for oscillation clock. the cha nnel 0(p34-p30) and channel 1(p 47-p44) share the monitor pin. [ ] please use p35/rcm for the evaluation purpose and disable the output while operati ng in an actual application to minimize the noise. ?port secondary function setting [ ] specify the secondary function for the port( refer to section 21.4 in the user?s manual). [ ] all the port 3 pins except p35/rcm ar e configured as pins dedicated to the rc- adc function during a/d conversion(refer to section 21.3.1. in the user?s manual). chapter 22 lcd driver ?bias [ ] 1/2 bias or [ ] 1/3 bias ?duty [ ] 1/1 to 1/5 duty ?com/seg [ ] ml610q407: 2com x 32seg [ ] ml610q407: 3com x 31seg [ ] ml610q407: 4com x 30seg [ ] ml610q407: 5com x 29seg [ ] ml610q408: 2com x 36seg [ ] ml610q408: 3com x 35seg [ ] ml610q408: 4com x 34seg [ ] ml610q408: 5com x 33seg [ ] ml610q409: 2com x 40seg [ ] ml610q409: 3com x 39seg [ ] ml610q409: 4com x 38seg [ ] ml610q409: 5com x 37seg
ml610q407/ml610q408/ml610q409 user's manual appendix e check list appendix e-4 ?external capacitor (1/3 bias, vdd = 1.6 to 3.6v, lcd without regulator) [ ] ca = 0.1uf (for vl1 pin), [ ] cc = 0.1uf (for vl3 pin) [ ] c12 = 0.47uf (for c1 pin to c2 pin) (1/3 bias, vdd = 2.4 to 3.6v, lcd without regulator) [ ] ca = 0.1uf (for vl1 pin), [ ] cb = 0.1uf (for vl2 pin) [ ] c12 = 0.47uf (for c1 pin to c2 pin) (1/3 bias, vdd = 1.2 to 3.6v, lcd with regulator) [ ] cb = 0.1uf (for vl2 pin), [ ] cc = 0.1uf (for vl3 pin) [ ] c12 = 0.47uf (for c1 pin to c2 pin) (1/2 bias, vdd = 1.6 to 3.6v, lcd without regulator) [ ] ca = 0.1uf (for vl1 pin) [ ] c12 = 0.47uf (for c1 pin to c2 pin) (1/2 bias, vdd = 1.25 to 3.6vlcd, with regulator) [ ] cc = 0.1uf (for vl3 pin) [ ] c12 = 0.47uf (for c1 pin to c2 pin) chapter 23 power supply circuit ?external capacitor [ ] cl = 0.47uf (for vddl pin) chapter 24 on-chip debug [ ] supply a voltage from 3.0v to 3.6v to the v dd pin when programming (erasing and writing) the flash rom with oki semiconductor development tool uease. [ ] please do not apply lsis being used for debugging to mass production. [ ] please validate the rom code on your production board without oki semiconductor development tool uease. appendix a sfr (specifi c function registers) ?initial value [ ] please confirm there are some sfrs have undefined initial value at reset ( refer to appendix a in the user?s manual ). appendix c electrical characteristics ?operating temperature [ ] -20c to +70c [ ] -40c to +85c ?operating voltage vs operating frequency [ ] please confirm the operating conditions. [ ] +1.25v to +3.6v (32.768khz: lo w-speed crystal oscillation clock operation) [ ] +1.25v to +3.6v (32.768khz to 500khz: low-speed crystal oscillation clock or built-in rc oscillation clock) [ ] +1.80v to +3.6v (32.768khz to 2mhz: low-speed crystal oscillation clock or built-in rc oscillation clock)
revision history
ml610q407/ml610q408/ml610q 409 user?s manual revision history r ? 1 revision history page document no. date previous edition current edition description feul610q409-01 nov. 7, 2010 ? ? formally edition 1.0

▲Up To Search▲

Price & Availability of ML610Q408P-NNNTBZ03A

	To Download ML610Q408P-NNNTBZ03A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .